专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06049851A Method and apparatus for checking cache coherency in a computer architecture 失效
标题翻译：用于在计算机体系结构中检查高速缓存一致性的方法和装置
公开(公告)号：US06049851A
公开(公告)日：2000-04-11
申请号：US196618
申请日：1994-02-14
申请人： William R. Bryg , Kenneth K. Chan , Eric Delano , John F. Shelton
发明人： William R. Bryg , Kenneth K. Chan , Eric Delano , John F. Shelton
IPC分类号： G06F12/08 , G06F9/34
CPC分类号： G06F12/0831
摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.
摘要翻译：具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在需要修改缓存。即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。

2. 发明授权

US5603004A Method for decreasing time penalty resulting from a cache miss in a multi-level cache system 失效
标题翻译：用于减少由多级缓存系统中的高速缓存未命中引起的时间损失的方法
公开(公告)号：US5603004A
公开(公告)日：1997-02-11
申请号：US196042
申请日：1994-02-14
申请人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
发明人： Gordon Kurpanek , Eric Delano , Michael A. Buckley , William R. Bryg
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0864 , G06F12/12 , G06F12/0862
摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.
摘要翻译：缓存系统缓冲存储在主存储器中并由处理器使用的数据。高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。第一个缓存是完全关联的。第二个缓存直接映射。第一个传输通道将数据线从主存储器传输到第一个缓存。第二传输信道将数据线从第一高速缓存传送到第二高速缓存。第三传送通道将数据线从第二高速缓存传送到主存储器。并行执行来自第一高速缓存和第二高速缓存的数据线的访问。

3. 发明申请

US20140173207A1 Power Gating A Portion Of A Cache Memory 有权
标题翻译：电源门控部分缓存内存
公开(公告)号：US20140173207A1
公开(公告)日：2014-06-19
申请号：US13715613
申请日：2012-12-14
申请人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
发明人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F1/32 , G06F1/3215 , G06F1/3225 , G06F1/3243 , G06F1/3287 , G06F12/0811 , G06F2212/1028 , Y02D10/13
摘要： In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。描述和要求保护其他实施例。

4. 发明申请

US20050240811A1 Core-level processor lockstepping 有权
标题翻译：核心级处理器锁步
公开(公告)号：US20050240811A1
公开(公告)日：2005-10-27
申请号：US10818975
申请日：2004-04-06
申请人： Kevin Safford , Christopher Lyles , Eric Delano
发明人： Kevin Safford , Christopher Lyles , Eric Delano
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1679 , G06F11/1641
摘要： A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供一种装置，其包括用于产生第一输出信号的第一微处理器核心; 第二微处理器核心，用于产生第二输出信号; 具有第一输入/输出端口的交换结构; 以及耦合在交换结构的第一输入/输出端口与第一和第二微处理器核心之间的锁步逻辑，以检测第一输出信号是否与第二输出信号不同。

5. 发明申请

US20050138478A1 Error detection method and system for processors that employ alternating threads 审中-公开
标题翻译：使用交替线程的处理器的错误检测方法和系统
公开(公告)号：US20050138478A1
公开(公告)日：2005-06-23
申请号：US10714258
申请日：2003-11-14
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1497 , G06F9/3861
摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.
摘要翻译：微处理器，包括检测软错误的机制。处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。比较硬件比较第一个执行周期的结果和第二个执行周期的结果。当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。处理器还包括提交单元，用于在结果相同时提交其中一个结果。

6. 发明授权

US08799586B2 Memory mirroring and migration at home agent 有权
标题翻译：内部镜像和迁移在本地代理
公开(公告)号：US08799586B2
公开(公告)日：2014-08-05
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

7. 发明授权

US08171121B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US08171121B2
公开(公告)日：2012-05-01
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

8. 发明申请

US20090019267A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 有权
公开(公告)号：US20090019267A1
公开(公告)日：2009-01-15
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
IPC分类号： G06F15/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

9. 发明申请

US20070067602A1 Mitigating context switch cache miss penalty 有权
标题翻译：减轻上下文切换缓存未命中
公开(公告)号：US20070067602A1
公开(公告)日：2007-03-22
申请号：US11228058
申请日：2005-09-16
申请人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
发明人： James Callister , Eric Delano , Rohit Bhatia , Shawn Walker , Mark Gibson
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0842
摘要： Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.
摘要翻译：描述了与减轻上下文切换高速缓存和TLB未命中的影响相关联的系统，方法，媒体和其他实施例。一个示例性系统实施例包括被配置为运行多处理虚拟存储器操作系统的处理器。处理器可以可操作地连接到存储器，并且可以包括被配置为存储TLB条目的高速缓存和翻译后备缓冲器（TLB）。示例性系统可以包括上下文控制逻辑，其被配置为选择性地将数据从TLB复制到数据存储器，用于从处理器交换出的第一进程，并且将数据从数据存储选择性地复制到TLB，以将第二进程交换到到处理器。

10. 发明授权

US07028167B2 Core parallel execution with different optimization characteristics to decrease dynamic execution path 有权
公开(公告)号：US07028167B2
公开(公告)日：2006-04-11
申请号：US10091084
申请日：2002-03-04
申请人： Donald C. Soltis, Jr. , Eric Delano
发明人： Donald C. Soltis, Jr. , Eric Delano
IPC分类号： G06F11/00
CPC分类号： G06F9/3891 , G06F9/3842 , G06F9/3851 , G06F9/3853 , G06F9/3885
摘要： The invention provides a processor with two or more parallel instruction paths for processing instructions. The instruction paths may be implemented with a plurality of cores on a common die. Instructions of the invention are preferably processed within a bundle of two or more instructions of a common program thread; and each of the instruction paths preferably forms a cluster to process bundled instructions. Each of the instruction paths has an array of pipelined execution units. Initially, two or more of the parallel instruction paths processes the same program thread (one or more bundles) through the execution units, but with different optimization characteristics set for each path. Assessment logic monitors the processing of the initial program thread through the execution units and selects the heuristics defining which path is in the lead. The other instruction paths are then reallocated, or synchronized, with the optimization characteristics of the lead instruction path, or with similarly optimized characteristics, to process other bundles of the program thread; preferably, the lead path continues processing of the initial thread without being disturbed. For other program threads, the process may repeat in processing like bundles through multiple instruction paths to identify the preferred heuristics; and then synchronizing the multiple instruction paths to the optimized characteristics to improve per thread performance.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式