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1. 发明授权

US08046639B1 Cycle accurate fault log modeling for a digital system 有权
标题翻译：为数字系统循环准确的故障日志建模
公开(公告)号：US08046639B1
公开(公告)日：2011-10-25
申请号：US12846653
申请日：2010-07-29
申请人： Grace Y. Nordin , Rakesh Mehta , Kenneth K. Chan
发明人： Grace Y. Nordin , Rakesh Mehta , Kenneth K. Chan
IPC分类号： G06F11/00
CPC分类号： G06F11/2268
摘要： A system and method for accurately modeling a fault log is provided for validating one or more elements of fault detection and logging logic for a real-time fault log of a digital system such as, for instance, a computer processor. The method includes injecting one or more known faults into a data path and/or a control path of the computer processor and spawning an individual tracking thread for each of the injected faults. The tracking threads may be synchronized at a predefined synchronization point that is selected as a function of a collective logging delay representing the time required for each of the injected faults to reach a real-time logging point within the computer processor. Once synchronized, the tracking threads may be input into a fault logging specification for fault behavior and/or system impact modeling and fault prioritization for use in generating a fault log model for comparison to the real-time fault log maintained within the computer processor.
摘要翻译：提供了一种用于对故障日志进行精确建模的系统和方法，用于验证数字系统（例如计算机处理器）的实时故障日志的故障检测和记录逻辑的一个或多个元件。该方法包括将一个或多个已知故障注入到计算机处理器的数据路径和/或控制路径中，并为每个注入的故障产生单独的跟踪线程。跟踪线程可以在预定义的同步点同步，该预定义同步点被选择为集体记录延迟的函数，其表示每个注入的故障到达计算机处理器内的实时记录点所需的时间。一旦同步，跟踪线程可以被输入到用于故障行为和/或系统影响建模和故障优先级的故障记录规范中，以用于生成故障日志模型以与计算机处理器内维护的实时故障日志进行比较。

2. 发明授权

US06049851A Method and apparatus for checking cache coherency in a computer architecture 失效
标题翻译：用于在计算机体系结构中检查高速缓存一致性的方法和装置
公开(公告)号：US06049851A
公开(公告)日：2000-04-11
申请号：US196618
申请日：1994-02-14
申请人： William R. Bryg , Kenneth K. Chan , Eric Delano , John F. Shelton
发明人： William R. Bryg , Kenneth K. Chan , Eric Delano , John F. Shelton
IPC分类号： G06F12/08 , G06F9/34
CPC分类号： G06F12/0831
摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.
摘要翻译：具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在需要修改缓存。即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。

3. 发明授权

US5978886A Method and apparatus for duplicating tag systems to maintain addresses of CPU data stored in write buffers external to a cache 失效
标题翻译：用于复制标签系统以维持存储在高速缓存外部的写入缓冲器中的CPU数据的地址的方法和装置
公开(公告)号：US5978886A
公开(公告)日：1999-11-02
申请号：US785371
申请日：1997-01-17
申请人： Julie W. Moncton , Kenneth K. Chan
发明人： Julie W. Moncton , Kenneth K. Chan
IPC分类号： G06F12/08 , G06F13/00 , G06F12/12
CPC分类号： G06F12/0831
摘要： An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of write transactions is issued to allow a subsystem that maintains duplicate cache tags to know in advance which write transactions are present in the CPU's buffers. Such information is used to keep duplicate tags for both the cache and any buffers that contain writes that are to be removed from the cache. The cache is preferably a direct mapped cache and the CPU preferably resides within a multiprocessor architecture. In the preferred embodiment, all write transactions are indirectly caused by a read transaction that is about to bring a line into the cache. Thus, a read transaction is issued by the CPU before the write transaction is issued. A field is added to the read transaction that indicates whether or not the read transaction has a corresponding line that must be written out of the cache and into a buffer, such that the duplicate tags duplicate both the CPU cache and the CPU write buffers.
摘要翻译：公开了一种用于复制标签地址以维持存储在高速缓存外部的写缓冲器中的中央处理单元（CPU）的数据的装置和方法。发出写入事务的预先通知，以允许维护重复的缓存标签的子系统事先知道CPU缓冲区中存在哪些写入事务。这些信息用于为缓存和包含要从缓存中删除的写入的任何缓冲区保留重复的标签。高速缓存优选地是直接映射高速缓存，并且CPU优选驻留在多处理器架构内。在优选实施例中，所有写入事务间接地由即将将高速缓存行引入的读取事务引起。因此，在发出写入事务之前，由CPU发出读取事务。读取事务中添加一个字段，该事务指示读取事务是否具有必须从高速缓存写入缓冲区的相应行，使得重复的标记同时复制CPU高速缓存和CPU写入缓冲区。

4. 发明授权

US5339440A Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested 失效
标题翻译：一个高速总线的等待状态机制，允许总线在请求总线等待后继续运行预设的循环次数
公开(公告)号：US5339440A
公开(公告)日：1994-08-16
申请号：US933434
申请日：1992-08-21
申请人： Edward M. Jacobs , Kenneth K. Chan , Thomas B. Alexander
发明人： Edward M. Jacobs , Kenneth K. Chan , Thomas B. Alexander
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/4217
摘要： The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.
摘要翻译：本发明提供了一种在数字计算机中等待总线的协议方法和用于实现该协议的装置。通过允许总线在等待命令被断言之后继续运行，计算机总线上的模块不需要立即响应等待命令。在等待期间的多个周期内，总线上的信息被定义为无效，等待期结束后在总线上驱动有效的数据。总线驱动器模块具有重播队列，用于在总线上播放驱动程序模块在等待期间在总线上驱动的数据（如果需要）。

5. 发明授权

US07943568B2 Antitumor agents 有权
标题翻译：抗肿瘤剂
公开(公告)号：US07943568B2
公开(公告)日：2011-05-17
申请号：US12088846
申请日：2005-09-30
申请人： Kenneth K. Chan , Jin Xiao
发明人： Kenneth K. Chan , Jin Xiao
IPC分类号： A61K38/00 , C12N5/00
CPC分类号： A61K38/15 , A61K38/12
摘要： Compounds and methods useful for the treatment of cancer in subjects in need of such treatment. The compounds are metabolites of the compound FK228 which have been identified as possessing HDAC inhibitory activity and anticancer properties. Further provided are compounds and methods for inducing apoptosis in cancer cells. Further provided are compounds and methods for inhibiting HDAC in cancer cells.
摘要翻译：可用于治疗需要这种治疗的受试者中的癌症的化合物和方法。这些化合物是化合物FK228的代谢物，其被鉴定为具有HDAC抑制活性和抗癌特性。还提供了诱导癌细胞凋亡的化合物和方法。还提供了用于抑制癌细胞中HDAC的化合物和方法。

6. 发明授权

US5708801A Apparatus and method for operating chips synchronously at speeds exceeding the bus speed 失效
标题翻译：以超过总线速度的速度同步运行芯片的装置和方法
公开(公告)号：US5708801A
公开(公告)日：1998-01-13
申请号：US744387
申请日：1996-11-07
申请人： James B. Williams , Kenneth K. Chan , John F. Shelton , Ehsan Rashid
发明人： James B. Williams , Kenneth K. Chan , John F. Shelton , Ehsan Rashid
IPC分类号： G06F1/06 , G06F13/42 , G06F1/12
CPC分类号： G06F1/06 , G06F13/4217
摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.
摘要翻译：一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。电路块包括用于在总线上接收和发送数据的接口电路。该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据，在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

7. 发明授权

US5530933A Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus 失效
标题翻译：通过按照在总线上发出的事务的顺序检查一致性来维持高速缓存一致性的多处理器系统
公开(公告)号：US5530933A
公开(公告)日：1996-06-25
申请号：US201463
申请日：1994-02-24
申请人： Craig R. Frink , William R. Bryg , Kenneth K. Chan , Thomas R. Hotchkiss , Robert D. Odineal , James B. Williams , Michael L. Ziegler
发明人： Craig R. Frink , William R. Bryg , Kenneth K. Chan , Thomas R. Hotchkiss , Robert D. Odineal , James B. Williams , Michael L. Ziegler
IPC分类号： G06F12/00 , G06F12/08 , G06F12/06
CPC分类号： G06F12/0831
摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.
摘要翻译：与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

8. 发明授权

US5524216A Coherent transaction ordering in multi-tiered bus system 失效
标题翻译：多层总线系统中的相干事务排序
公开(公告)号：US5524216A
公开(公告)日：1996-06-04
申请号：US242748
申请日：1994-05-13
申请人： Kenneth K. Chan , Thomas B. Alexander , Robert E. Naas , Julie W. Wu
发明人： Kenneth K. Chan , Thomas B. Alexander , Robert E. Naas , Julie W. Wu
IPC分类号： G06F12/08 , G06F12/10 , G06F13/36 , G06F13/40 , G06F15/173
CPC分类号： G06F13/4027
摘要： A computer system has a multi-tiered bus system. The multi-tiered bus system includes one or more local buses and a central bus connected to each local bus by a bus interface. In order to maintain one global view of transaction ordering, the processors on each local bus record bus transactions in an order on which the bus transactions appear on the central bus. To do this, bus transactions which are initiated on any local bus are forwarded to the central bus by the corresponding bus interface. The processors connected to the local bus do not record bus transactions when they are initiated on the local bus. Every transaction which occurs on the central bus is echoed back to every local bus by the corresponding bus interface. Each processor records bus transactions at the time they are echoed back to the local bus.
摘要翻译：计算机系统具有多层总线系统。多层总线系统包括一个或多个局部总线和通过总线接口连接到每个局部总线的中央总线。为了保持交易排序的一个全局视图，每个本地总线上的处理器按照总线事务在中央总线上出现的顺序记录总线事务。为此，在任何本地总线上启动的总线事务通过相应的总线接口转发到中央总线。连接到本地总线的处理器在本地总线上启动时不会记录总线事务。在中央总线上发生的每个事务通过相应的总线接口回传到每个局部总线。每个处理器在回传到本地总线时记录总线事务。

9. 发明授权

US4823338A Virtual local area network 失效
标题翻译：虚拟局域网
公开(公告)号：US4823338A
公开(公告)日：1989-04-18
申请号：US81081
申请日：1987-08-03
申请人： Kenneth K. Chan , Philip W. Hartmann , Scott P. Lamons , Terry G. Lyons , Argyrios C. Milonas
发明人： Kenneth K. Chan , Philip W. Hartmann , Scott P. Lamons , Terry G. Lyons , Argyrios C. Milonas
IPC分类号： H04L12/24 , H04L12/28 , H04L12/46 , H04J3/02 , H04J3/24
CPC分类号： H04L41/26 , H04L12/28 , H04L12/4641 , Y10S370/908
摘要： A system is disclosed for completing communication connections from end-users served by a connectionless (broadcast) type system in a manner which allows expansion of the calling area beyond the immediate physical limitations of the broadcast media. The system is based upon a device for mediating between the connectionless system and a connection oriented system. The device creates logical local area networks interconnectable by the connection oriented system. Calling user identification is used in conjunction with call completion data stored in a central memory for controlling all interconnections.

10. 发明授权

US4821170A Input/output system for multiprocessors 失效
标题翻译：多处理器输入/输出系统
公开(公告)号：US4821170A
公开(公告)日：1989-04-11
申请号：US40513
申请日：1987-04-17
申请人： David L. Bernick , Kenneth K. Chan , Wing M. Chan , Yie-Fong Dan , Duc M. Hoang , Zubair Hussain , Geoffrey I. Iswandhi , James E. Korpi , Martin W. Sanner , Jay A. Zwagerman , Steven G. Silverman , James E. Smith
发明人： David L. Bernick , Kenneth K. Chan , Wing M. Chan , Yie-Fong Dan , Duc M. Hoang , Zubair Hussain , Geoffrey I. Iswandhi , James E. Korpi , Martin W. Sanner , Jay A. Zwagerman , Steven G. Silverman , James E. Smith
IPC分类号： G06F11/18 , G06F9/52 , G06F11/00 , G06F11/10 , G06F13/12 , G06F13/28 , G06F13/40 , G06F15/16
CPC分类号： G06F13/28 , G06F13/122 , G06F13/4022 , G06F11/10
摘要： In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

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