专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07009604B2 Frame detector for use in graphics systems 有权
标题翻译：用于图形系统的帧检测器
公开(公告)号：US07009604B2
公开(公告)日：2006-03-07
申请号：US10199474
申请日：2002-07-19
申请人： William K. Chan , Nathaniel David Naegle
发明人： William K. Chan , Nathaniel David Naegle
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G5/12
摘要： One embodiment of a method of frame detection may involve storing data indicative of a pulse duration and a number of successive occurrences of pulses having that pulse duration for each of several different pulse durations detected within a first field of a composite synchronization signal. This process may be repeated for one or more other fields of the composite synchronization signal. The data stored for each of the fields may be compared, and a frame signal may be generated dependent on an outcome of said comparing.
摘要翻译：帧检测方法的一个实施例可以包括存储表示针对在复合同步信号的第一场内检测到的几个不同脉冲持续时间中的每一个的具有该脉冲持续时间的脉冲持续时间和连续出现脉冲数的数据。可以对复合同步信号的一个或多个其他字段重复该过程。可以对每个字段存储的数据进行比较，并且可以根据所述比较的结果生成帧信号。

2. 发明授权

US07266255B1 Distributed multi-sample convolution 有权
标题翻译：分布式多样本卷积
公开(公告)号：US07266255B1
公开(公告)日：2007-09-04
申请号：US10673087
申请日：2003-09-26
申请人： Michael A. Wasserman , Paul R. Ramsey , Nathaniel David Naegle
发明人： Michael A. Wasserman , Paul R. Ramsey , Nathaniel David Naegle
IPC分类号： G06K9/54 , G06K9/60 , G06K9/40 , G06K9/36 , G09G5/00 , G06F15/00 , G06F15/76
CPC分类号： G06F15/8053 , G06T3/4007 , G06T15/005
摘要： A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is responsible for a different interleaved region of screen space. Each chip performs part of the convolution process for a pixel and sends a partial result on to the next chip. The final chip completes the convolution and stores the filtered pixel. An alternate design interconnects chips in groups. The chips within a group operate in series, whereas the groups may operate in parallel.
摘要翻译：公开了一种用于分配卷积过程的多芯片系统。与在屏幕的不同部分工作的每个芯片并行工作的多个卷积芯片不同，新的设计使用串联工作的芯片。每个芯片负责屏幕空间的不同交错区域。每个芯片执行像素的卷积处理的一部分，并将部分结果发送到下一个芯片。最后的芯片完成卷积并存储滤波像素。另一种设计可以将芯片组合在一起。组内的芯片串联运行，而组可以并行运行。

3. 发明授权

US06650323B2 Graphics system having a super-sampled sample buffer and having single sample per pixel support 有权
标题翻译：图形系统具有超采样采样缓冲器并且每像素支持单个采样
公开(公告)号：US06650323B2
公开(公告)日：2003-11-18
申请号：US10194976
申请日：2002-07-12
申请人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
发明人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
IPC分类号： G06T1500
CPC分类号： G09G5/391 , G06T15/503 , G09G5/14 , G09G5/363 , G09G5/397 , G09G2340/0407 , G09G2354/00 , G09G2360/10 , G09G2360/121
摘要： A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer and may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. The graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to provide backwards compatibility with legacy systems.
摘要翻译：利用超采样采样缓冲器和用于刷新显示器的采样到像素计算单元的计算机图形系统。图形系统可以具有图形处理器，超采样采样缓冲器和采样到像素的计算单元。图形处理器将样本呈现到样本缓冲器中，并且可以利用在每个对象的基础上指定像素的属性的窗口ID。窗口ID可以指定样本模式，过滤器类型，颜色属性或源属性中的一个或多个。样本模式可以包括每像素模式的单个样本和每像素模式的多个采样。图形系统可以进一步可操作以为屏幕的某些窗口生成每个像素的单个样本，以便向遗留系统提供向后兼容性。

4. 发明授权

US06496187B1 Graphics system configured to perform parallel sample to pixel calculation 有权
标题翻译：图形系统配置为执行并行采样到像素计算
公开(公告)号：US06496187B1
公开(公告)日：2002-12-17
申请号：US09472940
申请日：1999-12-27
申请人： Michael F. Deering , Nathaniel David Naegle , Scott R. Nelson
发明人： Michael F. Deering , Nathaniel David Naegle , Scott R. Nelson
IPC分类号： G06T1500
CPC分类号： G06T5/20 , G06T11/001 , G06T11/40 , G06T15/503
摘要： A graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. The graphics system may include a graphics processor, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processor is configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer is configured to store the plurality of samples for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical or horizontal stripe of the image, or a rectangular portion of the image. Each region may overlap the other regions of the image to prevent visual aberrations.
摘要翻译：被配置为利用采样缓冲器和多个平行的样本到像素计算单元的图形系统，其中采样像素计算单元被配置为并行地访问样本缓冲器的不同部分。图形系统可以包括图形处理器，采样缓冲器和多个采样到像素的计算单元。图形处理器被配置为接收一组三维图形数据并且基于图形数据呈现多个采样。样本缓冲器被配置为存储用于样本到像素计算单元的多个样本，其被配置为从样本缓冲器接收和过滤样本以创建输出像素。每个样本到像素计算单元被配置为生成与图像的不同区域相对应的像素。该区域可以是图像的垂直或水平条纹，或图像的矩形部分。每个区域可能与图像的其他区域重叠以防止视觉异常。

5. 发明授权

US06654021B2 Multi-channel, demand-driven display controller 有权
公开(公告)号：US06654021B2
公开(公告)日：2003-11-25
申请号：US09861461
申请日：2001-05-18
申请人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , David C. Kehlet , Nathaniel David Naegle , Steven Te-Chun Yu , Glenn Gracon
IPC分类号： G06F1318
CPC分类号： G09G5/12 , G06F3/1431 , G09G5/395 , G09G2360/123
摘要： A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

6. 发明授权

US07737994B1 Large-kernel convolution using multiple industry-standard graphics accelerators 有权
标题翻译：使用多个行业标准图形加速器的大内核卷积
公开(公告)号：US07737994B1
公开(公告)日：2010-06-15
申请号：US10673088
申请日：2003-09-26
申请人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
发明人： Michael A. Wasserman , Ewa M. Kubalska , Nathaniel David Naegle , Brian D. Emberling , Paul R. Ramsey , Mark E. Pascual
IPC分类号： G06F15/80 , G09G5/00 , G06K9/64
CPC分类号： G06T11/40 , G06T1/20 , G09G5/14 , G09G5/363 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： A multi-chip system and method are disclosed that utilizes a plurality of graphics pipelines to perform large kernel convolution. Each graphics pipeline includes a standard rendering unit and a video data convolve unit. Each video data convolve unit receives video pixel data from the video output of the standard rendering unit. The video data convolve units are connected in a chain. Each group of one or more video data convolve units in the chain convolves the video pixel data received by the group. The last video data convolve unit in the chain outputs a stream of convolved pixels.
摘要翻译：公开了利用多个图形管线来执行大的内核卷积的多芯片系统和方法。每个图形流水线包括标准渲染单元和视频数据卷积单元。每个视频数据卷积单元从标准渲染单元的视频输出接收视频像素数据。视频数据卷积单元连接在一起。链中的每一组一个或多个视频数据卷积单元卷积由该组接收的视频像素数据。链中的最后一个视频数据卷积单元输出一个卷积像素流。

7. 发明授权

US07292207B1 Computing blending functions for the tiling of overlapped video projectors 有权
标题翻译：计算重叠视频投影机平铺的混合功能
公开(公告)号：US07292207B1
公开(公告)日：2007-11-06
申请号：US10929115
申请日：2004-08-27
申请人： Nathaniel David Naegle , Clayton W. Castle
发明人： Nathaniel David Naegle , Clayton W. Castle
IPC分类号： G09G5/00
CPC分类号： H04N9/3188 , G09G3/001 , G09G2320/0233 , G09G2340/10 , H04N9/3147 , H04N9/3182
摘要： A system for correcting the intensities of pixels supplied to a projector. An image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors. The system includes: a first unit configured to generate a horizontal scaling value; a second unit configured to generate a vertical scaling value; a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient, and a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel. The first unit and second unit compute their respective scaling values in a way that allows for regions whose boundaries non-aligned in the vertical direction.
摘要翻译：一种用于校正提供给投影仪的像素的强度的系统。由投影仪产生的图像具有由图像与一个或多个其它投影仪产生的一个或多个其它图像重叠而形成的多个区域。该系统包括：第一单元，被配置为生成水平缩放值; 第二单元，被配置为生成垂直缩放值; 配置为乘以水平缩放值和垂直缩放值以获得缩放系数的第一乘法器，以及被配置为将输入像素的分量乘以缩放系数的一个或多个附加乘法器的集合，以确定输出像素的分量。第一单元和第二单元以允许其边界在垂直方向上不对齐的区域的方式计算它们各自的缩放值。

8. 发明授权

US06952214B2 Method for context switching a graphics accelerator comprising multiple rendering pipelines 有权
标题翻译：用于上下文切换包括多个渲染管线的图形加速器的方法
公开(公告)号：US06952214B2
公开(公告)日：2005-10-04
申请号：US10194446
申请日：2002-07-12
申请人： Nathaniel David Naegle , William E. Sweeney, Jr. , Wayne A. Morse
发明人： Nathaniel David Naegle , William E. Sweeney, Jr. , Wayne A. Morse
IPC分类号： G06F9/46 , G06T15/00 , G06T1/20
CPC分类号： G06F9/461 , G06T15/005 , G06T2210/52
摘要： A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network and the memory of each rendering pipeline. The media processor in each rendering pipeline may direct the saving of state information of the corresponding rendering pipeline to the corresponding memory in response to receiving a corresponding context switch indication. A first of the media processors initiates the transfer of a resume token to the scheduling network through the corresponding rendering pipeline if the context switch occurs during an ordered processing mode. The scheduling network unblocks one or more rendering pipelines other than the first rendering pipeline in response to receiving the resume token.
摘要翻译：包括多个渲染管线和调度网络的图形系统。每个渲染流水线耦合到调度网络，并且包括媒体处理器，渲染单元和存储器。通信总线可以耦合调度网络和每个渲染管线的存储器。响应于接收到相应的上下文切换指示，每个渲染流水线中的媒体处理器可以将相应呈现流水线的状态信息保存到对应的存储器。如果在有序处理模式期间发生上下文切换，则第一媒体处理器通过相应的渲染流水线启动将简历令牌传送到调度网络。响应于接收到恢复令牌，调度网络解除阻塞除第一渲染流水线之外的一个或多个渲染管线。

9. 发明授权

US06816162B2 Data management to enable video rate anti-aliasing convolution 有权
标题翻译：数据管理使视频速率反锯齿卷积
公开(公告)号：US06816162B2
公开(公告)日：2004-11-09
申请号：US10200087
申请日：2002-07-19
申请人： Nimita J. Taneja , Nathaniel David Naegle , Michael F. Deering
发明人： Nimita J. Taneja , Nathaniel David Naegle , Michael F. Deering
IPC分类号： G06F1300
CPC分类号： G06T11/40 , G06T5/20
摘要： A system and method is disclosed for management of sample data to enable video rate anti-aliasing convolution. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g. 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g. 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.
摘要翻译：公开了一种用于管理样本数据以实现视频速率抗混叠卷积的系统和方法。样本数据可以同时从采样缓冲器移动到bin扫描线高速缓存，并且从bin扫描线高速缓存移动到N 2个处理器存储器单元的阵列（例如，对于N = 5为25）。像素数据可以从可以近似于像素位置的中心的N×N样本仓阵列卷积。由于每个样本箱包含Ns / b个样本，因此可以针对每个像素滤波Ns / bxN <2个样本（例如N = 5和Ns / b = 16的400）。每个处理器存储器单元将一个样本仓的样本数据卷积在NxN样本仓阵列中，并支持各种滤波器功能。像素数据可以输出到实时视频数据流。

10. 发明授权

US06795076B2 Graphics system with real-time convolved pixel readback 有权
标题翻译：具有实时卷积像素回读的图形系统
公开(公告)号：US06795076B2
公开(公告)日：2004-09-21
申请号：US09894068
申请日：2001-06-28
申请人： Michael F. Deering , Nathaniel David Naegle
发明人： Michael F. Deering , Nathaniel David Naegle
IPC分类号： G06F1516
CPC分类号： G06T1/20 , G06F3/14 , G06T15/005
摘要： A graphics system comprising a control unit and a series of calculation units coupled together in a closed chain by a segmented communication bus. The calculation unit collaboratively generate one or more video signals. Each calculation unit is programmably assigned to contribute its locally-generated pixels to one of the video streams. The control unit sends a frame readback request to a selected one of the calculation units through the segmented communication bus. The frame readback request specifies some subset of the pixels in one of the video streams for readback to the control unit. In response to the frame readback request, the selected calculation unit transmits the subset of pixels of the specified video stream to the control unit, and the control unit forwards the subset of pixels to a target memory block (e.g. in system memory of a host computer or memory within the graphics system).
摘要翻译：一种图形系统，包括控制单元和通过分段通信总线在闭合链中耦合在一起的一系列计算单元。计算单元协同生成一个或多个视频信号。可编程地分配每个计算单元以将其本地生成的像素贡献给一个视频流。控制单元通过分段通信总线向所选择的一个计算单元发送帧回读请求。帧回读请求指定一个视频流中的像素的一些子集，用于回读到控制单元。响应于帧回读请求，所选择的计算单元将指定的视频流的像素的子集发送到控制单元，并且控制单元将像素子集转发到目标存储器块（例如，在主计算机的系统存储器中）或图形系统内的内存）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式