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1. 发明授权

US07245540B2 Controller for delay locked loop circuits 有权
标题翻译：延迟锁定环路控制器
公开(公告)号：US07245540B2
公开(公告)日：2007-07-17
申请号：US09874898
申请日：2001-06-05
申请人： William Jones , Wen Li
发明人： William Jones , Wen Li
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/22
摘要： A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.
摘要翻译：提供了一种控制存储器件中的延迟锁定环（DLL）的方法。 DLL根据外部时钟信号产生内部时钟信号。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。该方法涉及防止DLL在诸如活动模式，读取模式或刷新模式的存储器件的操作模式期间响应于操作条件的变化，例如存储器件的电源电压的变化。

2. 发明授权

US06809974B2 Controller for delay locked loop circuits 失效
标题翻译：延迟锁定环路控制器
公开(公告)号：US06809974B2
公开(公告)日：2004-10-26
申请号：US10231513
申请日：2002-08-29
申请人： William Jones , Wen Li , Mark R. Thomann , Timothy B. Cowles , Daniel R. Loughmiller
发明人： William Jones , Wen Li , Mark R. Thomann , Timothy B. Cowles , Daniel R. Loughmiller
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C29/02
摘要： A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
摘要翻译：提供了一种在测试模式期间监视存储器件中的延迟锁定环（DLL）的特性的方法。 DLL根据外部时钟信号产生内部时钟信号。外部和内部时钟信号通常是同步的。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。该方法涉及防止DLL响应于在测试模式期间存储器件的电源电压变化的操作条件的改变。

3. 发明授权

US06901013B2 Controller for delay locked loop circuits 失效
标题翻译：延迟锁定环路控制器
公开(公告)号：US06901013B2
公开(公告)日：2005-05-31
申请号：US09874894
申请日：2001-06-05
申请人： William Jones , Wen Li , Mark R. Thomann , Timothy B. Cowles , Daniel R. Loughmiller
发明人： William Jones , Wen Li , Mark R. Thomann , Timothy B. Cowles , Daniel R. Loughmiller
IPC分类号： G11C7/22 , G11C29/02 , G11C7/00
CPC分类号： G11C7/222 , G11C7/22 , G11C29/02
摘要： A method of monitoring the characteristics of a delay locked loop (DLL) in a memory device during a test mode is provided. The DLL generates an internal clock signal based on an external clock signal. The external and internal clock signals are normally synchronized. DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during a test mode.
摘要翻译：提供了一种在测试模式期间监视存储器件中的延迟锁定环（DLL）的特性的方法。 DLL根据外部时钟信号产生内部时钟信号。外部和内部时钟信号通常是同步的。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。该方法涉及防止DLL响应于在测试模式期间存储器件的电源电压变化的操作条件的改变。

4. 发明授权

US06819603B2 Method of controlling a delay locked loop 失效
标题翻译：控制延迟锁定环路的方法
公开(公告)号：US06819603B2
公开(公告)日：2004-11-16
申请号：US10231512
申请日：2002-08-29
申请人： William Jones , Wen Li
发明人： William Jones , Wen Li
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22
摘要： A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.
摘要翻译：提供了一种控制存储器件中的延迟锁定环（DLL）的方法。 DLL根据外部时钟信号产生内部时钟信号。 DLL不断响应存储器件的工作状态的变化，以保持外部和内部时钟同步。该方法涉及防止DLL在诸如活动模式，读取模式或刷新模式的存储器件的操作模式期间响应于操作条件的变化，例如存储器件的电源电压的变化。

5. 发明授权

US09506603B2 Metal hydrides with embedded metal structures for hydrogen storage 有权
标题翻译：具有嵌入金属结构的金属氢化物用于储氢
公开(公告)号：US09506603B2
公开(公告)日：2016-11-29
申请号：US13615988
申请日：2012-09-14
申请人： Wen Li , John J. Vajo , Alan J. Jacobsen , Mei Cai , Martin P. Sulic
发明人： Wen Li , John J. Vajo , Alan J. Jacobsen , Mei Cai , Martin P. Sulic
IPC分类号： F17C11/00
CPC分类号： F17C11/005 , Y02E60/321 , Y10T29/49826
摘要： One illustrative embodiment includes materials and devices including an integrated hydrogen storage structure including a plurality of continuously connected thermally conductive elongated members, the elongated members including continuously connected openings between the elongated members; and, a metal hydride material contacting the elongated members and disposed within the connected openings and surrounding the elongated members.
摘要翻译：一个说明性实施例包括包括包括多个连续连接的导热细长构件的集成氢存储结构的材料和装置，细长构件包括在细长构件之间的连续连接的开口; 以及金属氢化物材料，其与细长构件接触并且设置在连接的开口内并围绕细长构件。

6. 发明授权

US09126834B2 Hydrogen storage materials 有权
标题翻译：储氢材料
公开(公告)号：US09126834B2
公开(公告)日：2015-09-08
申请号：US12615524
申请日：2009-11-10
申请人： Wen Li , Adam F. Gross , Alan J. Jacobsen , John J. Vajo
发明人： Wen Li , Adam F. Gross , Alan J. Jacobsen , John J. Vajo
IPC分类号： C01B31/02 , B82Y30/00 , C01B3/00 , B01J20/20 , B01J20/02
CPC分类号： C01B31/02 , B01J20/0203 , B01J20/20 , B82Y30/00 , C01B3/0021 , C01B3/0026 , C01B3/0031 , C01B3/0036 , C01B3/0042 , C01B3/0047 , C01B3/0057 , C01B3/0068 , C01B3/0084 , C01B32/05 , Y02E60/325 , Y02E60/327
摘要： A hydrogen storage material has been developed that comprises a metal hydride material embedded into a carbon microstructure that generally exhibits a greater bulk thermal conductivity than the surrounding bulk metal hydride material.
摘要翻译：已经开发了一种储氢材料，其包含嵌入到碳微结构中的金属氢化物材料，其通常表现出比周围的体金属氢化物材料更大的体积导热系数。

7. 发明授权

US08764966B2 Electrochemical process and device for hydrogen generation and storage 失效
标题翻译：用于氢气发生和储存的电化学工艺和装置
公开(公告)号：US08764966B2
公开(公告)日：2014-07-01
申请号：US13293432
申请日：2011-11-10
申请人： John J. Vajo , Wen Li , Ping Liu , Frederick E. Pinkerton
发明人： John J. Vajo , Wen Li , Ping Liu , Frederick E. Pinkerton
IPC分类号： C25B1/02 , C25B11/04
CPC分类号： C25B1/02 , C25D11/04 , H01M8/04216 , H01M8/0656
摘要： Both the reaction of hydride-forming compositions with hydrogen to form hydrides, and the decomposition of such hydrides to release hydrogen may be promoted electrochemically. These reactions may be conducted reversibly, and if performed in a suitable cell, the cell will serve as a hydrogen storage and release device.
摘要翻译：氢化物形成组合物与氢形成氢化物的反应以及这种氢化物分解以释放氢，可以电化学地促进。这些反应可以可逆地进行，并且如果在合适的电池中进行，则电池将用作储氢和释放装置。

8. 发明申请

US20140125398A1 Driver Integrated Circuit 有权
标题翻译：驱动器集成电路
公开(公告)号：US20140125398A1
公开(公告)日：2014-05-08
申请号：US14122623
申请日：2012-05-24
申请人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
发明人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175 , H01L2224/48137 , H01L2924/181 , H03F1/52 , H03F3/195 , H03F3/211 , H03F3/3022 , H03F2200/189 , H03K19/017509 , H01L2924/00012
摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).
摘要翻译：提供可以输出超过工艺耐压的电压并满足所需设备性能（高速和高电压）的驱动器集成电路的结构。差分输入电路，电平移位电路和输出电路通过相同的工艺制造并且被分配和布置在具有不同衬底电位（子电位）的三个或更多个芯片上。通过对芯片的基板设置不同的施加电压，可以提供大于工艺耐受电压的输出电压（参见图2）。

9. 发明授权

US08495341B2 Instruction length based cracking for instruction of variable length storage operands 有权
标题翻译：指令长度为可变长度存储操作数指令的破解
公开(公告)号：US08495341B2
公开(公告)日：2013-07-23
申请号：US12707163
申请日：2010-02-17
申请人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
发明人： Fadi Busaba , Brian Curran , Bruce Giamei , Christian Jacobi , Wen Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30149 , G06F9/3016 , G06F9/3017
摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.
摘要翻译：一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。接收至少一个可变操作数长度指令。分析至少一个可变操作数长度指令。基于分析来识别可变操作数长度指令中的至少一个操作数的长度。所述至少一个可变操作数长度指令被组织成一组操作单元。执行操作单元的集合。所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

10. 发明申请

US20130168796A1 PHOTODIODE ARRAYS AND METHODS OF FABRICATION 审中-公开
标题翻译：光电子阵列和制造方法
公开(公告)号：US20130168796A1
公开(公告)日：2013-07-04
申请号：US13343146
申请日：2012-01-04
申请人： Abdelaziz Ikhlef , Wen Li
发明人： Abdelaziz Ikhlef , Wen Li
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14658 , A61B6/032 , A61B6/037 , A61B6/4233 , H01L23/481 , H01L27/1446 , H01L27/14636 , H01L27/14663 , H01L31/105 , H01L2224/0401 , H01L2224/0557 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
摘要： Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface. The photodiode array also includes a plurality of refilled conductive vias through the silicon wafer, wherein the refilled conductive vias have a doping type different than the doping type of the substrate, and an interface between the refilled conductive vias and the substrate form diode junctions. The photodiode array further includes a patterned doped layer on the first surface overlapping the refilled conductive vias, wherein the patterned doped layer defines an array of photodiodes.
摘要翻译：提供了光电二极管阵列和制造方法。一个光电二极管阵列包括具有第一表面和相对的第二表面的硅晶片。光电二极管阵列还包括通过硅晶片的多个重新填充的导电通孔，其中重新填充的导电通孔具有不同于衬底的掺杂类型的掺杂类型，并且再填充的导电通孔和衬底之间的界面形成二极管结。光电二极管阵列还包括在重新填充的导电通孔上的第一表面上的图案化掺杂层，其中图案化掺杂层限定光电二极管阵列。

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