专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06807186B2 Architectures for a single-stage grooming switch 有权
标题翻译：单阶段美容开关架构
公开(公告)号：US06807186B2
公开(公告)日：2004-10-19
申请号：US10052233
申请日：2002-01-17
申请人： William J. Dally , John Edmondson , Donald A. Priore , Ephrem Wu , John W. Poulton
发明人： William J. Dally , John Edmondson , Donald A. Priore , Ephrem Wu , John W. Poulton
IPC分类号： H04L1228
CPC分类号： H04L49/405 , H04Q3/521
摘要： A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.
摘要翻译：提供单级梳理开关，用于在时域和空间域中切换多路复用业务流，如SONET STS-48。特别地，交换机实现分布式解复用架构，用于在减少的布局大小的任何输入时隙之间切换到任何输出时隙。此外，分布式解复用架构导致低延迟与纳秒级的输出排列的重新配置相关联。

2. 发明申请

US20110310691A1 Multi-Port Memory Using Single-Port Memory Cells 失效
标题翻译：使用单端口存储单元的多端口存储器
公开(公告)号：US20110310691A1
公开(公告)日：2011-12-22
申请号：US13153392
申请日：2011-06-04
申请人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
发明人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
IPC分类号： G11C8/16
CPC分类号： G11C8/16 , G06F12/06 , G11C7/1075 , Y02D10/13
摘要： A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.
摘要翻译：可操作以提供多端口功能的存储器包括形成第一存储器阵列的多个单端口存储器单元。第一存储器阵列被组织成多个存储器组，每个存储器组包括单端口存储器单元的相应子集。存储器还包括包括多个多端口存储器单元的第二存储器阵列，并且可操作以跟踪存储在第一存储器阵列中相应位置中的数据的状态信息。至少一个高速缓存存储器与第一存储器阵列连接，并且可操作地存储用于解决第一存储器阵列中的并发读和写访问冲突的数据。存储器包括控制器，其操作：接收状态信息并根据状态信息确定存储在第一存储器阵列中的数据的有效性; 以控制数据存储在存储器中以避免高速缓冲存储器中的数据溢出的方式; 并在同一个内存周期内解决第一个内存阵列中的并发读写访问冲突。

3. 发明申请

US20100238938A1 HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP 有权
标题翻译：高速分组FIFO输出缓冲器，用于开关转换
公开(公告)号：US20100238938A1
公开(公告)日：2010-09-23
申请号：US12729231
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： H04L12/56
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括从交换结构接收m个N位数据部分的第一逻辑模块，m个N位数据部分包括一个或多个数据分组的一个或多个N位数据字。多个单端口存储器存储所接收的数据部分。每个单端口存储器具有分段宽度W / S的S个部分的宽度W，其中W / S与N相关。第二逻辑模块从单端口存储器提供一个或多个N位数据字，对应于到所接收的m个N位数据部分。在时钟周期的顺序中，数据部分以循环方式从单端口存储器的相应段交替传送，并且对于每个时钟周期，第二逻辑模块构造从单端口存储器读出的数据。

4. 发明授权

US08374050B2 Multi-port memory using single-port memory cells 失效
标题翻译：使用单端口存储单元的多端口存储器
公开(公告)号：US08374050B2
公开(公告)日：2013-02-12
申请号：US13153392
申请日：2011-06-04
申请人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
发明人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
IPC分类号： G11C8/00 , G06F13/00 , G06F13/28
CPC分类号： G11C8/16 , G06F12/06 , G11C7/1075 , Y02D10/13
摘要： A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.
摘要翻译：可操作以提供多端口功能的存储器包括形成第一存储器阵列的多个单端口存储器单元。第一存储器阵列被组织成多个存储器组，每个存储器组包括单端口存储器单元的相应子集。存储器还包括包括多个多端口存储器单元的第二存储器阵列，并且可操作以跟踪存储在第一存储器阵列中相应位置中的数据的状态信息。至少一个高速缓存存储器与第一存储器阵列连接，并且可操作地存储用于解决第一存储器阵列中的并发读和写访问冲突的数据。存储器包括控制器，其操作：接收状态信息并根据状态信息确定存储在第一存储器阵列中的数据的有效性; 以控制数据存储在存储器中以避免高速缓冲存储器中的数据溢出的方式; 并在同一个内存周期内解决第一个内存阵列中的并发读写访问冲突。

5. 发明授权

US08352669B2 Buffered crossbar switch system 有权
标题翻译：缓冲交叉开关系统
公开(公告)号：US08352669B2
公开(公告)日：2013-01-08
申请号：US12430438
申请日：2009-04-27
申请人： Ephrem Wu , Ting Zhou , Steven Pollock
发明人： Ephrem Wu , Ting Zhou , Steven Pollock
IPC分类号： G06F13/00
CPC分类号： H04L49/254 , H04L49/101 , H04L49/252 , H04L49/3027 , H04L49/3045 , H04L49/508 , H04Q3/0004 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13322
摘要： Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.
摘要翻译：描述的实施例提供数据模块之间的数据传输。使用至少两个交叉开关，其中每个交叉开关的输入节点和输出节点耦合到对应的数据模块。第i个交叉开关具有Mi输出开关结构的Ni输入，其中Ni和Mi是大于1的正整数。每个交叉开关包括每个输入节点处的输入缓冲器，交换结构的每个交叉点处的交叉点缓冲器，以及每个输出节点处的输出缓冲器。输入缓冲器具有根据第一调度算法从输入缓冲器读取数据分组的仲裁器。仲裁器根据第二调度算法从交叉点缓冲队列读取数据包。输出节点接收从一个或多个相应的交叉点缓冲器提供的数据分组段。

6. 发明申请

US20100333057A1 Parametric Data-Based Process Monitoring for Adaptive Body Bias Control 失效
标题翻译：用于自适应身体偏差控制的参数化基于数据的过程监控
公开(公告)号：US20100333057A1
公开(公告)日：2010-12-30
申请号：US12493658
申请日：2009-06-29
申请人： Robin Tang , Ephrem Wu , Tezaswi Raja
发明人： Robin Tang , Ephrem Wu , Tezaswi Raja
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G11C11/4074
摘要： Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.
摘要翻译：公开了用于提供自适应体偏置控制的系统和方法的各种实施例。一个实施例包括用于自适应体偏置控制的方法。一种这样的方法包括：对与芯片设计相关联的参数数据进行建模; 建模与芯片设计相关的关键路径数据; 根据芯片设计提供芯片; 将参数数据和关键路径数据存储在芯片上的存储器中; 从芯片上的参数传感器读取数据; 基于来自参数传感器和存储的关键路径和参数数据的数据，确定优化的体节点电压以降低芯片的功耗而不引起定时故障; 并根据优化的体节点电压调整体节点电压。

7. 发明申请

US20100238937A1 HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT 失效
标题翻译：高速分组FIFO输入缓冲器，用于开关和转换开关
公开(公告)号：US20100238937A1
公开(公告)日：2010-09-23
申请号：US12729226
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： H04L12/56 , G06F3/00 , G06F12/00 , G06F12/08 , G06F5/14
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括多个寄存器，其被配置为接收分组中的数据的N位部分和多个单端口存储器，每个存储器的宽度W分割成宽度W / S的S个部分。第一逻辑模块耦合到寄存器和单端口存储器并且接收数据的N位部分和寄存器的输出。耦合到单端口存储器的第二逻辑模块构造从单端口存储器读出的数据。在时钟周期的顺序中，N位数据部分从第一逻辑模块交替地传送到单端口存储器的一部分，并且对于每个时钟周期，第二逻辑模块以输出宽度构建数据输出数据包基于m的加速因子。

8. 发明授权

US08438641B2 Security protocol processing for anti-replay protection 失效
标题翻译：用于防重放保护的安全协议处理
公开(公告)号：US08438641B2
公开(公告)日：2013-05-07
申请号：US12980489
申请日：2010-12-29
申请人： Vojislav Vukovic , Brian Vanderwarn , Nikola Radovanovic , Ephrem Wu
发明人： Vojislav Vukovic , Brian Vanderwarn , Nikola Radovanovic , Ephrem Wu
IPC分类号： G06F7/04
CPC分类号： H04L63/1466
摘要： Described embodiments provide a network processor that includes a security protocol processor to prevent replay attacks on the network processor. A memory stores security associations for anti-replay operations. A pre-fetch module retrieves an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has a range of sequence numbers. When the network processor receives a data packet, the security hardware accelerator determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. Depending on the value, the data packet is either received or accepted. The anti-replay window might be updated to reflect the receipt of the most recent data packet.
摘要翻译：所描述的实施例提供一种包括安全协议处理器以防止对网络处理器的重放攻击的网络处理器。内存存储用于反重放操作的安全关联。预取模块检索对应于网络处理器的数据流的反重播窗口。反播放窗口具有一系列序列号。当网络处理器接收到数据分组时，安全硬件加速器相对于反重放窗口的序列号范围的最小值和最大值确定接收到的序列号的值。取决于值，数据包被接收或接受。可以更新反重播窗口以反映最近的数据包的接收。

9. 发明授权

US08181147B2 Parametric data-based process monitoring for adaptive body bias control 失效
标题翻译：用于自适应体偏置控制的参数化基于数据的过程监控
公开(公告)号：US08181147B2
公开(公告)日：2012-05-15
申请号：US12493658
申请日：2009-06-29
申请人： Robin Tang , Ephrem Wu , Tezaswi Raja
发明人： Robin Tang , Ephrem Wu , Tezaswi Raja
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G11C11/4074
摘要： Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.
摘要翻译：公开了用于提供自适应体偏置控制的系统和方法的各种实施例。一个实施例包括用于自适应体偏置控制的方法。一种这样的方法包括：对与芯片设计相关联的参数数据进行建模; 建模与芯片设计相关的关键路径数据; 根据芯片设计提供芯片; 将参数数据和关键路径数据存储在芯片上的存储器中; 从芯片上的参数传感器读取数据; 基于来自参数传感器和存储的关键路径和参数数据的数据，确定优化的体节点电压以降低芯片的功耗而不引起定时故障; 并根据优化的体节点电压调整体节点电压。

10. 发明授权

US07430202B2 System and method of tributary time-space switching 失效
标题翻译：支流时空切换的系统与方法
公开(公告)号：US07430202B2
公开(公告)日：2008-09-30
申请号：US10802114
申请日：2004-03-15
申请人： Ephrem Wu
发明人： Ephrem Wu
IPC分类号： H04L12/50 , H04Q11/00 , G06F9/34 , G06F9/26 , G06F12/00
CPC分类号： H04J3/1611 , H04J2203/001
摘要： A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are capable of being individually switched in space and time. A write controller causes input columns of the input data stream to be written to a common buffer according to a write pointer. In parallel, a read controller causes the input columns to be read from the common buffer to output columns of an output data stream according to a read pointer. For each of the output columns, the read pointer selects an input column from a limited portion of the buffer that contains a set of the input columns that are capable of being switched in time to the corresponding output column according to a communication protocol.
摘要翻译：提供了一种具有低存储器要求的支路时空开关和切换方法。开关包括多个输入和输出。每个输入接收从外部输入链路承载能够在空间和时间中单独切换的支路有效载荷的输入数据流。写入控制器使得输入数据流的输入列根据写指针被写入公共缓冲器。并行地，读取控制器使得从公共缓冲器读取输入列，以根据读取指针输出输出数据流的列。对于每个输出列，读指针从缓冲器的受限部分中选择一个输入列，该输入列包含能够根据通信协议及时切换到相应的输出列的一组输入列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式