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1. 发明授权

US08374050B2 Multi-port memory using single-port memory cells 失效
标题翻译：使用单端口存储单元的多端口存储器
公开(公告)号：US08374050B2
公开(公告)日：2013-02-12
申请号：US13153392
申请日：2011-06-04
申请人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
发明人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
IPC分类号： G11C8/00 , G06F13/00 , G06F13/28
CPC分类号： G11C8/16 , G06F12/06 , G11C7/1075 , Y02D10/13
摘要： A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.
摘要翻译：可操作以提供多端口功能的存储器包括形成第一存储器阵列的多个单端口存储器单元。第一存储器阵列被组织成多个存储器组，每个存储器组包括单端口存储器单元的相应子集。存储器还包括包括多个多端口存储器单元的第二存储器阵列，并且可操作以跟踪存储在第一存储器阵列中相应位置中的数据的状态信息。至少一个高速缓存存储器与第一存储器阵列连接，并且可操作地存储用于解决第一存储器阵列中的并发读和写访问冲突的数据。存储器包括控制器，其操作：接收状态信息并根据状态信息确定存储在第一存储器阵列中的数据的有效性; 以控制数据存储在存储器中以避免高速缓冲存储器中的数据溢出的方式; 并在同一个内存周期内解决第一个内存阵列中的并发读写访问冲突。

2. 发明申请

US20110310691A1 Multi-Port Memory Using Single-Port Memory Cells 失效
标题翻译：使用单端口存储单元的多端口存储器
公开(公告)号：US20110310691A1
公开(公告)日：2011-12-22
申请号：US13153392
申请日：2011-06-04
申请人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
发明人： Ting Zhou , Ephrem Wu , Sheng Liu , Hyuck Jin Kwon
IPC分类号： G11C8/16
CPC分类号： G11C8/16 , G06F12/06 , G11C7/1075 , Y02D10/13
摘要： A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.
摘要翻译：可操作以提供多端口功能的存储器包括形成第一存储器阵列的多个单端口存储器单元。第一存储器阵列被组织成多个存储器组，每个存储器组包括单端口存储器单元的相应子集。存储器还包括包括多个多端口存储器单元的第二存储器阵列，并且可操作以跟踪存储在第一存储器阵列中相应位置中的数据的状态信息。至少一个高速缓存存储器与第一存储器阵列连接，并且可操作地存储用于解决第一存储器阵列中的并发读和写访问冲突的数据。存储器包括控制器，其操作：接收状态信息并根据状态信息确定存储在第一存储器阵列中的数据的有效性; 以控制数据存储在存储器中以避免高速缓冲存储器中的数据溢出的方式; 并在同一个内存周期内解决第一个内存阵列中的并发读写访问冲突。

3. 发明申请

US20100238938A1 HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP 有权
标题翻译：高速分组FIFO输出缓冲器，用于开关转换
公开(公告)号：US20100238938A1
公开(公告)日：2010-09-23
申请号：US12729231
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： H04L12/56
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括从交换结构接收m个N位数据部分的第一逻辑模块，m个N位数据部分包括一个或多个数据分组的一个或多个N位数据字。多个单端口存储器存储所接收的数据部分。每个单端口存储器具有分段宽度W / S的S个部分的宽度W，其中W / S与N相关。第二逻辑模块从单端口存储器提供一个或多个N位数据字，对应于到所接收的m个N位数据部分。在时钟周期的顺序中，数据部分以循环方式从单端口存储器的相应段交替传送，并且对于每个时钟周期，第二逻辑模块构造从单端口存储器读出的数据。

4. 发明申请

US20100238937A1 HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT 失效
标题翻译：高速分组FIFO输入缓冲器，用于开关和转换开关
公开(公告)号：US20100238937A1
公开(公告)日：2010-09-23
申请号：US12729226
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： H04L12/56 , G06F3/00 , G06F12/00 , G06F12/08 , G06F5/14
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括多个寄存器，其被配置为接收分组中的数据的N位部分和多个单端口存储器，每个存储器的宽度W分割成宽度W / S的S个部分。第一逻辑模块耦合到寄存器和单端口存储器并且接收数据的N位部分和寄存器的输出。耦合到单端口存储器的第二逻辑模块构造从单端口存储器读出的数据。在时钟周期的顺序中，N位数据部分从第一逻辑模块交替地传送到单端口存储器的一部分，并且对于每个时钟周期，第二逻辑模块以输出宽度构建数据输出数据包基于m的加速因子。

5. 发明授权

US08473657B2 High speed packet FIFO output buffers for switch fabric with speedup 有权
标题翻译：高速数据包FIFO输出缓冲区用于交换矩阵加速
公开(公告)号：US08473657B2
公开(公告)日：2013-06-25
申请号：US12729231
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括从交换结构接收m个N位数据部分的第一逻辑模块，m个N位数据部分包括一个或多个数据分组的一个或多个N位数据字。多个单端口存储器存储所接收的数据部分。每个单端口存储器具有分段宽度W / S的S个部分的宽度W，其中W / S与N相关。第二逻辑模块从单端口存储器提供一个或多个N位数据字，对应于到所接收的m个N位数据部分。在时钟周期的顺序中，数据部分以循环方式从单端口存储器的相应段交替传送，并且对于每个时钟周期，第二逻辑模块构造从单端口存储器读出的数据。

6. 发明授权

US08243737B2 High speed packet FIFO input buffers for switch fabric with speedup and retransmit 失效
标题翻译：用于交换结构的高速分组FIFO输入缓冲区，具有加速和重传
公开(公告)号：US08243737B2
公开(公告)日：2012-08-14
申请号：US12729226
申请日：2010-03-22
申请人： Ting Zhou , Sheng Liu , Ephrem Wu
发明人： Ting Zhou , Sheng Liu , Ephrem Wu
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/10
摘要： Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
摘要翻译：所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出（FIFO）缓冲器。 FIFO缓冲器包括多个寄存器，其被配置为接收分组中的数据的N位部分和多个单端口存储器，每个存储器的宽度W分割成宽度W / S的S个部分。第一逻辑模块耦合到寄存器和单端口存储器并且接收数据的N位部分和寄存器的输出。耦合到单端口存储器的第二逻辑模块构造从单端口存储器读出的数据。在时钟周期的顺序中，N位数据部分从第一逻辑模块交替地传送到单端口存储器的一段，并且对于每个时钟周期，第二逻辑模块以输出宽度构建数据输出数据包基于m的加速因子。

7. 发明授权

US08359466B2 Security association prefetch for security protcol processing 有权
标题翻译：安全关联预取用于安全性质的处理
公开(公告)号：US08359466B2
公开(公告)日：2013-01-22
申请号：US13097213
申请日：2011-04-29
申请人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
发明人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
IPC分类号： H04L29/06 , G06F9/00
CPC分类号： H04L63/0485 , H04L63/164 , H04L63/20 , H04L69/12 , H04L69/32
摘要： Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.
摘要翻译：描述的实施例提供一种网络处理器，其包括用于具有安全关联（SA）的分组的分级安全处理的安全协议处理器。 SA请求模块计算SA的地址。 SA被提取到本地内存。从本地存储器中的SA读取SA预取控制字（SPCW）。 SPCW识别SA的一个或多个区域以及一个或多个区域的相关联的阶段。 SPCW解析器从SPCW生成一个或多个阶段SPCW（SSPCW）。每个SSPCW存储在相应的SSPCW寄存器中。预取模块根据预定义的算法为每个SSPCW寄存器提供服务。预取模块读取所请求的SA区域，并将所请求的SA区域提供给相应阶段，用于分组的相关部分的分段安全处理。

8. 发明申请

US20120278615A1 SECURTIY ASSOCIATION PREFETCH FOR SECURITY PROTCOL PROCESSING 有权
标题翻译：安全机构处理安全协会
公开(公告)号：US20120278615A1
公开(公告)日：2012-11-01
申请号：US13097213
申请日：2011-04-29
申请人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
发明人： Sheng Liu , Nikola Radovanovic , Ephrem Wu
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L63/164 , H04L63/20 , H04L69/12 , H04L69/32
摘要： Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet.
摘要翻译：描述的实施例提供一种网络处理器，其包括用于具有安全关联（SA）的分组的分级安全处理的安全协议处理器。 SA请求模块计算SA的地址。 SA被提取到本地内存。从本地存储器中的SA读取SA预取控制字（SPCW）。 SPCW识别SA的一个或多个区域以及一个或多个区域的相关联的阶段。 SPCW解析器从SPCW生成一个或多个阶段SPCW（SSPCW）。每个SSPCW存储在相应的SSPCW寄存器中。预取模块根据预定义的算法为每个SSPCW寄存器提供服务。预取模块读取所请求的SA区域，并将所请求的SA区域提供给相应阶段，用于分组的相关部分的分段安全处理。

9. 发明申请

US20050059429A1 Inter-communication mobile phone set 审中-公开
标题翻译：互通手机套
公开(公告)号：US20050059429A1
公开(公告)日：2005-03-17
申请号：US10662413
申请日：2003-09-16
申请人： Sheng Liu , Sheng Liu
发明人： Sheng Liu , Sheng Liu
IPC分类号： H04M1/05 , H04M1/21 , H04M1/725 , H04M1/00
CPC分类号： H04M1/72513 , H04M1/05 , H04M1/21
摘要： An inter-communication mobile phone set comprises a main phone, a SIM card and a plurality of sub-phones. The main phone is one of a multi-user main phone, a personal main phone, and an in-car main phone; the multi-user main phone, personal main phone and in-car main phone searching for sub-phones automatically and the frequencies thereof so that signals of the main phone and sub-phones can inter-communicate to one another. The main phone is connected to other main phone through a SIM card. The sub-phone has a type selected from one of a simple type, a pen-form sub-phone, a neck-tie form phone, a watch form sub-phone, a breast-suspending sub-phone, an ear-phone form sub-phone, a hat form sub-phone. The sub-phone is built in one of a portable audio, a translator, a notebook computer, a PDA, a personal computer expansion card, a pocket, a game machine, a camera.
摘要翻译：一种互通式移动电话机包括主电话机，SIM卡和多个子电话机。主要手机是多用户主要手机，个人主要手机和车载主要手机之一，多用户主电话，个人主电话和车内主要手机自动搜索子电话及其频率，使得主电话和子电话的信号可以相互通信。主要手机通过SIM卡连接到其他主要手机。子电话具有从简单类型，笔式子电话，领带形式电话，表格子电话，挂号子电话，耳机形式之一中选择的类型子手机，帽子形式的分机。子电话内置在便携式音频，翻译器，笔记本电脑，PDA，个人计算机扩展卡，口袋，游戏机，照相机之一中。

10. 发明申请

US20050279449A1 Positioning method in manufacturing process of electronic elements 审中-公开
公开(公告)号：US20050279449A1
公开(公告)日：2005-12-22
申请号：US10872003
申请日：2004-06-21
申请人： Sheng Liu , Sheng Liu
发明人： Sheng Liu , Sheng Liu
IPC分类号： H05K13/04 , B32B31/00
CPC分类号： H05K13/0469
摘要： A positioning method in the manufacturing process of electronic elements comprises the steps of: dropping positioning glue on a working table; drying the positioning glue; placing a work piece upon the positioning glue so as to fix the work piece; performing other processes; checking whether the positioning glue is available; if yes, repeating the process for another work piece; and if not, cleaning the positioning glue from the work piece and repeating the process for the work piece.

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