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1. 发明授权

US5153880A Field-programmable redundancy apparatus for memory arrays 失效
标题翻译：用于存储阵列的现场可编程冗余设备
公开(公告)号：US5153880A
公开(公告)日：1992-10-06
申请号：US491749
申请日：1990-03-12
申请人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
发明人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/789 , G11C29/835 , G11C29/838
摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over the standard signal paths with standard voltage levels of the integrated circuit semiconductor memory array. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundance apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.
摘要翻译：公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。用户通过具有集成电路半导体存储器阵列的标准电压电平的标准信号路径与冗余设备进行通信。冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。现场可编程冗余装置可以包括诸如EEPROM的非易失性存储装置，以存储具有冗余存储器单元的主存储器单元的替换。在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

2. 发明授权

US5161157A Field-programmable redundancy apparatus for memory arrays 失效
标题翻译：用于存储器阵列的现场可编程冗余装置
公开(公告)号：US5161157A
公开(公告)日：1992-11-03
申请号：US802005
申请日：1991-11-27
申请人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
发明人： William H. Owen , John Caywood , Joseph Drori , James Jaffe , Isao Nojima , Jeffrey Sung , Ping Wang
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/789 , G06F11/006 , G11C29/835 , G11C29/838
摘要： A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM's, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.
摘要翻译：公开了一种用于集成电路半导体存储器阵列的现场可编程冗余装置。本发明允许用户在集成电路存储器阵列处于现场时用冗余存储器单元替换有缺陷的存储单元。用户通过集成电路半导体存储器阵列的标准信号路径与标准电压电平与冗余设备进行通信。冗余设备在存储器阵列的一个或多个地址和数据线上检测预定的代码序列，以进入特殊的冗余重新配置模式。在重新配置模式中，冗余设备提供关于冗余存储器单元的可用性和功能的信息，并且使得用户能够用所选择的冗余存储器单元来替换有缺陷的存储器单元。现场可编程冗余设备可以包括非易失性存储器装置，例如EEPROM，用于存储具有冗余存储器单元的主存储器单元的替换。在重新配置模式中，第二预定代码序列的检测导致重新配置模式被退出。

3. 发明授权

US5974579A Efficient built-in self test for embedded memories with differing address spaces 失效
标题翻译：对于具有不同地址空间的嵌入式存储器进行高效内置自检
公开(公告)号：US5974579A
公开(公告)日：1999-10-26
申请号：US707062
申请日：1996-09-03
申请人： Yervant David Lepejian , Hrant Marandjian , Hovhannes Ghukasyan , John Caywood , Lawrence Kraus
发明人： Yervant David Lepejian , Hrant Marandjian , Hovhannes Ghukasyan , John Caywood , Lawrence Kraus
IPC分类号： G11C29/20 , G11C29/28 , G01R31/28
CPC分类号： G11C29/20 , G11C29/28
摘要： A built-in self test (BIST) circuit for an integrated circuit tests one or more embedded memories by writing data to each memory address, reading it back out, and then comparing the input and output data to see if they match. The BIST circuit includes one or more data generators for supplying a sequence of data to be written to the various addresses of each memory and one or more identical address generators, each for supplying addresses to a separate embedded memory during read and write operations. Though the memories may have differently sized address spaces, all address generators generate a similar address sequence having a range of address values as large or larger than the address space of the largest memory. During each memory write cycle, a separate filter checks the address output of each address generator to determine whether the address is within the address space of the corresponding memory. If so, the BIST circuit writes the current data output of a data generator to that address of the memory. If not, the BIST circuit ignores the current address and data outputs of the address and data generators and repeats the write operation it performed during a next preceding memory write cycle, writing the same data to the same valid memory address. The BIST circuit makes a similar address substitution during write operation. This allows the BIST circuit to use identical address generators for all memories regardless of the size of the memory being tested.
摘要翻译：用于集成电路的内置自测（BIST）电路通过将数据写入每个存储器地址进行一个或多个嵌入式存储器的测试，将其读出，然后比较输入和输出数据，看它们是否匹配。 BIST电路包括一个或多个数据生成器，用于提供要写入每个存储器的各个地址的数据序列以及一个或多个相同的地址生成器，每个地址生成器用于在读取和写入操作期间向单独的嵌入式存储器提供地址。虽然存储器可能具有不同大小的地址空间，但是所有地址生成器生成类似的地址序列，其地址值的范围大于或大于最大存储器的地址空间。在每个存储器写入周期期间，单独的滤波器检查每个地址发生器的地址输出，以确定地址是否在相应存储器的地址空间内。如果是这样，BIST电路将数据发生器的当前数据输出写入存储器的地址。如果不是，则BIST电路忽略地址和数据发生器的当前地址和数据输出，并重复在下一个前一个存储器写周期期间执行的写操作，将相同的数据写入相同的有效存储器地址。 BIST电路在写操作期间进行类似的地址替换。这允许BIST电路为所有存储器使用相同的地址生成器，而不管正在测试的存储器的大小。

4. 发明授权

US06451652B1 Method for forming an EEPROM cell together with transistor for peripheral circuits 有权
标题翻译：用于与外围电路晶体管一起形成EEPROM单元的方法
公开(公告)号：US06451652B1
公开(公告)日：2002-09-17
申请号：US09656730
申请日：2000-09-07
申请人： John Caywood , Gregorio Spadea
发明人： John Caywood , Gregorio Spadea
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.
摘要翻译：公开了一种与外围电路晶体管一起形成EEPROM单元的方法。该方法导致具有在电极边缘附近保留的预定量的材料，从而形成延伸超过电极侧面的短距离的结构。还公开了用于与外围电路的晶体管一起形成三层EEPROM单元的附加方法，这导致三层被限制为覆盖电极和在衬底表面上延伸的小的邻近区域。也可以在沿着所述电极的边缘的氧化物层的侧壁中蚀刻两个肩部。

5. 发明授权

US5235544A Flash EPROM cell and method for operating same 失效
标题翻译：闪存EPROM单元及其操作方法
公开(公告)号：US5235544A
公开(公告)日：1993-08-10
申请号：US611423
申请日：1990-11-09
申请人： John Caywood
发明人： John Caywood
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/16 , G11C16/14 , Y10S257/90
摘要： A flash EPROM cell may be erased by placing a negative voltage on the control gate of a flash EPROM cell having spaced apart source and drain regions in a semiconductor substrate, and having a floating gate, a control gate and a sidewall gate, while biasing the drain at a positive voltage.
摘要翻译：闪存EPROM单元可以通过在半导体衬底中具有间隔开的源极和漏极区域的闪存EPROM单元的控制栅极上施加负电压而被擦除，并且具有浮置栅极，控制栅极和侧壁栅极，同时偏置在正电压下漏极。

6. 发明授权

US06745370B1 Method for selecting an optimal level of redundancy in the design of memories 有权
标题翻译：在存储器设计中选择最佳冗余度的方法
公开(公告)号：US06745370B1
公开(公告)日：2004-06-01
申请号：US09616806
申请日：2000-07-14
申请人： Julie Segal , David Lepejian , John Caywood
发明人： Julie Segal , David Lepejian , John Caywood
IPC分类号： G06F1750
CPC分类号： G11C29/72 , H01L22/22
摘要： A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.
摘要翻译：一种用于确定在存储器集成电路中采用的冗余单元的数量的方法。确定了一系列缺陷尺寸的集成电路中每个工艺层上的故障的关键区域，以及故障电路对输入测试刺激的电响应的特征。确定两个签名的统计频率分布，用于每个处理层上的缺陷大小的比率以及所选择的签名的组合的出现。确定不同数量的冗余单元的签名分布的比率以及不同数量的冗余单元中的每一个的管芯区域的比例。每个晶片的可用裸片的数量由签名分布和管芯面积确定。选择使每个晶片可用裸片数量最大化的冗余度。

7. 发明授权

US06534816B1 Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell 有权
标题翻译：将电荷注入到非易失性存储单元的浮动栅上的方法和装置
公开(公告)号：US06534816B1
公开(公告)日：2003-03-18
申请号：US09516400
申请日：2000-03-01
申请人： John Caywood
发明人： John Caywood
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator which may employ a graded band gap disposed adjacent said grid electrode, and a floating gate disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element. A memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.
摘要翻译：隧穿电荷注入器包括导电注入器电极，邻近导电注入器电极设置的栅极绝缘体，邻近所述栅极绝缘体设置的栅电极，可使用邻近所述栅电极设置的渐变带隙的保持绝缘体，邻近所述保持绝缘体。在隧穿电荷注入器中，电荷从导电注入器电极注入到浮动栅上。当导电注入器电极相对于栅格电极被负偏压时，电子注入到浮动栅极上，并且当导电注入器电极相对于栅电极被正偏置时，将空穴注入到浮置栅极上。隧道电荷注入器用于具有浮置栅极的非易失性存储元件的非易失性存储单元，例如浮置栅极MOS晶体管。在非易失性存储单元中，隧穿电荷注入器的浮置栅极耦合到或形成非易失性存储元件的浮置栅极的一部分。隧道电荷注入器用于将电荷注入到非易失性存储元件的浮置栅极上。存储器件包括非易失性存储器单元的阵列，其中每个存储器单元包括具有诸如浮动栅极MOS晶体管的浮动栅极的非易失性存储器元件和具有浮置栅极的隧道电荷注入器，该浮置栅极耦合到浮置栅极的浮动栅极非易失性存储元件或形成非易失性存储元件的浮置栅极的一部分。

8. 发明授权

US06411545B1 Non-volatile latch 有权
标题翻译：非易失性锁存器
公开(公告)号：US06411545B1
公开(公告)日：2002-06-25
申请号：US09713635
申请日：2000-11-14
申请人： John Caywood
发明人： John Caywood
IPC分类号： G11C1604
CPC分类号： G11C14/00
摘要： A non-volatile latch comprises first and second read/write bias nodes and first and second a complementary output nodes. First and second first conductivity type MOS transistors have sources coupled to a first voltage potential. A drain of the first MOS transistor is coupled to the first complementary output node and a drain of the second MOS transistor is coupled to the second complementary output node. Each of the first and second MOS transistors have a gate cross coupled to the drain of the other one of the first and second MOS transistor. A source of a third MOS transistor is coupled to the first read/write bias node and a source of a fourth MOS transistor is coupled to the second read/write bias node. A drain of the third MOS transistor is coupled to the first complementary output node and a drain of the fourth MOS transistor is coupled to the second complementary output node. Each of the third and fourth MOS transistors have a gate cross coupled to the source of the other one of the third and fourth MOS transistors.
摘要翻译：非易失性锁存器包括第一和第二读/写偏置节点，第一和第二补码输出节点。第一和第二第一导电型MOS晶体管具有耦合到第一电压电位的源。第一MOS晶体管的漏极耦合到第一互补输出节点，并且第二MOS晶体管的漏极耦合到第二互补输出节点。第一和第二MOS晶体管中的每一个具有栅极交叉耦合到第一和第二MOS晶体管中的另一个的漏极。第三MOS晶体管的源极耦合到第一读/写偏置节点，并且第四MOS晶体管的源极耦合到第二读/写偏置节点。第三MOS晶体管的漏极耦合到第一互补输出节点，第四MOS晶体管的漏极耦合到第二互补输出节点。第三和第四MOS晶体管中的每一个具有耦合到第三和第四MOS晶体管中的另一个的源极的栅极交叉。

9. 发明授权

US6096093A Method for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuits 失效
标题翻译：使用检查数据提高集成电路制造中步进电路的吞吐量的方法
公开(公告)号：US6096093A
公开(公告)日：2000-08-01
申请号：US985624
申请日：1997-12-05
申请人： John Caywood , David Y Lepejian
发明人： John Caywood , David Y Lepejian
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , G03F7/70533 , G03F7/7065 , H01L22/12
摘要： A method for managing stepper operations required during the manufacturing of an integrated circuit die having at least one known defect, as determined by inspection, comprises the steps of determining, based upon an analysis of the connectivity and defect information relating to the die having at least one known defect a probability of failure to each at least one known defect and eliminating from stepper operations any die having at least one fatal defect.
摘要翻译：一种用于管理制造具有至少一个已知缺陷的集成电路管芯所需的步进操作的方法，如通过检查确定的，包括以下步骤：基于至少具有至少具有模具的连接性和缺陷信息的分析来确定一个已知的缺陷是每个至少一个已知缺陷的故障概率，并且从步进操作中消除任何具有至少一个致命缺陷的管芯。

10. 发明授权

US06780656B2 Correction of overlay offset between inspection layers 有权
标题翻译：检查层之间的覆盖偏移校正
公开(公告)号：US06780656B2
公开(公告)日：2004-08-24
申请号：US09972742
申请日：2001-10-05
申请人： David Muradian , John Caywood , Brian Duffy , Julie Segal
发明人： David Muradian , John Caywood , Brian Duffy , Julie Segal
IPC分类号： H01L2166
CPC分类号： G01N21/95607 , G03F7/70633 , G03F7/7065 , G06T7/0004 , G06T7/41 , G06T2207/10012 , G06T2207/30148 , H01L21/67288 , H01L22/20
摘要： A method for determining between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of at least three origins based on the selected pairs of data sets.
摘要翻译：用于确定用于至少三个不同缺陷检查空间的坐标系的至少三个起点之间的方法。该方法包括：收集跨越缺陷检查空间的多组数据; 过滤数据集以将引入噪声的点去除到相关计算中; 确定不同的数据集是否显示相关性; 选择显示大于或等于度量的相关性的数据集对; 以及基于所选择的数据集对计算至少三个起始点的坐标偏移。

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