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1. 发明授权

US5860129A Data processing system for writing an external device and method therefor 失效
标题翻译：用于写入外部设备的数据处理系统及其方法
公开(公告)号：US5860129A
公开(公告)日：1999-01-12
申请号：US534764
申请日：1995-09-27
申请人： William C. Moyer , Charles Kirtland , John H. Arends
发明人： William C. Moyer , Charles Kirtland , John H. Arends
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1689
摘要： A data processing system (10) provides flexibility in interfacing with both a variety of memory devices (56, 58) and external peripheral devices (58). A control register (94) is provided for dynamically controlling a timing relationship between read and write accesses executed by the data processing system. A first set of bits (WP) stored in the control register determines an amount of time a write enable signal is asserted to indicate a length of time required to write a data value to an external device. By recognizing the difference in the timing requirements for read and write operations among different external peripheral devices and memories, as well as the difference in the timing requirements of read and write operations on the same external device, the first set of bits of the control register uses the best timing scheme available to increase the efficiency of the data processing system.
摘要翻译：数据处理系统（10）提供与各种存储设备（56,58）和外部外围设备（58）的接口的灵活性。提供控制寄存器（94），用于动态地控制由数据处理系统执行的读和写访问之间的定时关系。存储在控制寄存器中的第一组位（WP）确定写使能信号被断言以指示将数据值写入外部设备所需的时间长度的时间量。通过识别不同的外部设备和存储器之间的读取和写入操作的时序要求的差异以及同一外部设备上的读取和写入操作的时序要求的差异，控制寄存器的第一组位使用可用的最佳时序方案来提高数据处理系统的效率。

2. 发明授权

US5752267A Data processing system for accessing an external device during a burst mode of operation and method therefor 失效
标题翻译：用于在突发操作模式期间访问外部设备的数据处理系统及其方法
公开(公告)号：US5752267A
公开(公告)日：1998-05-12
申请号：US534763
申请日：1995-09-27
申请人： William C. Moyer , Charles Kirtland , John H. Arends
发明人： William C. Moyer , Charles Kirtland , John H. Arends
IPC分类号： G06F12/00 , G06F13/42 , G06F15/78 , G06F13/00
CPC分类号： G06F13/4243
摘要： A data processing system (10) flexibly interfaces with both a variety of memory devices and external peripheral devices. A control register (94) is provided for dynamically controlling a timing relationship for read and write accesses executed by the system. A first set of bits (PA) in the control register provides timing control for an initial amount of time required to read a first data value from an external device. A second set of bits (SA) in the control register provides timing control for each successive amount of time required to read a successive data value from the external device.
摘要翻译：数据处理系统（10）与各种存储设备和外部外围设备灵活地接口。提供控制寄存器（94），用于动态地控制由系统执行的读取和写入访问的定时关系。控制寄存器中的第一组位（PA）提供从外部设备读取第一数据值所需的初始时间量的定时控制。控制寄存器中的第二组位（SA）为从外部设备读取连续数据值所需的每个连续的时间量提供定时控制。

3. 发明授权

US06751724B1 Method and apparatus for instruction fetching 失效
标题翻译：指令取出方法和装置
公开(公告)号：US06751724B1
公开(公告)日：2004-06-15
申请号：US09552118
申请日：2000-04-19
申请人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
发明人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
IPC分类号： G06F930
CPC分类号： G06F9/3814 , G06F9/3802
摘要： Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.
摘要翻译：本发明的实施例涉及在数据处理系统中的指令取出。一个方面涉及一种数据处理器（202），用于执行指令并根据取出大小从存储器（208）获取指令。该数据处理器（202）包括用于接收指令的第一输入（212），解码指令的控制逻辑（402）以及耦合到第一输入（212）和控制逻辑（400）的指令流水线（400）。指令流水线（400）响应于第一信号（214）将获取大小设置为第一大小和第二大小中的一个。因此，数据处理器（202）允许基于所访问设备的特性来改变指令获取策略，以便实现改进的性能。

4. 发明授权

US06401196B1 Data processor system having branch control and method thereof 失效
标题翻译：具有分支控制的数据处理器系统及其方法
公开(公告)号：US06401196B1
公开(公告)日：2002-06-04
申请号：US09100669
申请日：1998-06-19
申请人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
发明人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
IPC分类号： G06F912
CPC分类号： G06F9/324 , G06F9/325
摘要： A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.
摘要翻译：公开了在分支地址处取出反向分支地址指令的具体实现。后向分支指令具有一个偏移值，用于定义程序循环的大小。计数器设置为与循环大小成比例的值。在一个示例中，计数器设置为偏移值。当执行循环的每个指令时，计数器被修改以指示循环中剩余的指令数。当循环当前通过中没有指令时，计数器将重置为偏移值，并重复循环直到遇到终止条件。作为实现的一部分，在循环执行之前读取并存储分支指令之后的指令。

5. 发明授权

US5375216A Apparatus and method for optimizing performance of a cache memory in a data processing system 失效
标题翻译：用于优化数据处理系统中的高速缓冲存储器的性能的装置和方法
公开(公告)号：US5375216A
公开(公告)日：1994-12-20
申请号：US844011
申请日：1992-02-28
申请人： William C. Moyer , John H. Arends , Christopher E. White , Keith E. Diefendorff
发明人： William C. Moyer , John H. Arends , Christopher E. White , Keith E. Diefendorff
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/02
CPC分类号： G06F9/30047 , G06F12/0802 , G06F12/0804 , G06F12/0862 , G06F9/30043 , G06F9/30181 , G06F9/383 , G06F9/3842 , G06F9/3863 , G06F2212/6028
摘要： A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.
摘要翻译：在数据处理器（20）中实现用于允许对高速缓存存储器的更大用户控制的电路。高速缓存控制指令已被实现以在数据高速缓存单元（24）的数据高速缓存（54）中执行触摸负载，刷新和分配操作。控制指令由指令高速缓存单元（26）和定序器（34）两者解码，以向加载/存储单元（28）提供必要的控制和地址信息。加载/存储单元（28）排序每个指令的执行，并且在适当的时间点向数据高速缓存单元（24）提供必要的控制和地址信息。缓存控制逻辑（60）随后处理地址和控制信息以提供执行每个高速缓存控制指令所必需的外部信号。此外，高速缓存控制逻辑（60）提供允许用户知道何时执行高速缓存事务的外部传输代码信号。

6. 发明授权

US07117346B2 Data processing system having multiple register contexts and method therefor 有权
公开(公告)号：US07117346B2
公开(公告)日：2006-10-03
申请号：US10159386
申请日：2002-05-31
申请人： William C. Moyer , John H. Arends
发明人： William C. Moyer , John H. Arends
IPC分类号： G06F12/00
CPC分类号： G06F9/30123 , G06F9/30134
摘要： A data processing system having multiple register contexts is described. One embodiment of the present invention uses a user programmable context control register for each of the multiple register contexts to allow for the mapping of portions of an alternate register context into a current register context. The context control register may also be used to provide for the sharing of common stack pointers among multiple register contexts. Therefore, when operating in a current register context, the context control register may be used to access portions of an alternate register context in place of accessing corresponding portions of the current register context.

7. 发明授权

US06591378B1 Debug controller in a data processor and method therefor 有权
标题翻译：数据处理器中的调试控制器及其方法
公开(公告)号：US06591378B1
公开(公告)日：2003-07-08
申请号：US09507740
申请日：2000-02-22
申请人： John H. Arends , Jeffrey W. Scott , William C. Moyer
发明人： John H. Arends , Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F1100
CPC分类号： G06F11/362 , G06F9/321 , G06F9/3863
摘要： A method for debug control in a pipelined data processor where an offset is determined for the program counter (PC) based on the state of the pipeline. The offset is subtracted from the PC value at the end of a debug session. The resultant PC value restarts fetching of a last unsuccessfully completed instruction. If the offset indicates a change to the PC value, the instruction register is adjusted to a nop to allow the pipeline to restart execution after the last successfully completed instruction. In one embodiment, the state of the machine is preserved prior to exception handling.
摘要翻译：一种用于流水线数据处理器中的调试控制的方法，其中基于流水线的状态为程序计数器（PC）确定偏移量。在调试会话结束时从PC值中减去偏移量。所得到的PC值将重新获取最后一个未成功完成的指令。如果偏移量表示PC值的变化，则指令寄存器被调整为nop，以允许管道在上次成功完成指令之后重新启动。在一个实施例中，在异常处理之前保持机器的状态。

8. 发明授权

US06560712B1 Bus arbitration in low power system 有权
标题翻译：低功率系统中的总线仲裁
公开(公告)号：US06560712B1
公开(公告)日：2003-05-06
申请号：US09440857
申请日：1999-11-16
申请人： John H. Arends , William C. Moyer , Steven L. Schwartz
发明人： John H. Arends , William C. Moyer , Steven L. Schwartz
IPC分类号： G06F132
CPC分类号： G06F1/3253 , G06F1/3203 , G06F13/364 , Y02D10/151
摘要： Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.
摘要翻译：在包括处理器核心和耦合到处理器核心的系统电路的数据处理系统中节省功率。用于节省功率的第一种方法包括由处理器和系统电路进入低功率状态，并且当处理器核保持在低功率状态时由处理器使能总线仲裁。一个实施例进一步设想了一种通过授权总线对请求设备的访问并且由处理器核对其响应地进入功率节省模式来节省功率的方法。然后在处理器核心保持在省电模式的同时执行总线操作。另一个实施例考虑了一种调试数据处理系统的方法，其中调试状态由处理器和系统电路输入，此后，当处理器核心保持在调试状态时，总线仲裁由处理器启用。

9. 发明授权

US07188262B2 Bus arbitration in low power system 有权
标题翻译：低功率系统中的总线仲裁
公开(公告)号：US07188262B2
公开(公告)日：2007-03-06
申请号：US10376816
申请日：2003-02-28
申请人： John H. Arends , William C. Moyer , Steven L. Schwartz
发明人： John H. Arends , William C. Moyer , Steven L. Schwartz
IPC分类号： G06F1/00 , G06F13/36
CPC分类号： G06F1/3253 , G06F1/3203 , G06F13/364 , Y02D10/151
摘要： Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.
摘要翻译：在包括处理器核心和耦合到处理器核心的系统电路的数据处理系统中节省功率。用于节省功率的第一种方法包括由处理器和系统电路进入低功率状态，并且当处理器核保持在低功率状态时由处理器使能总线仲裁。一个实施例进一步设想了一种通过授权总线对请求设备的访问并且由处理器核对其响应地进入功率节省模式来节省功率的方法。然后在处理器核心保持在省电模式的同时执行总线操作。另一个实施例考虑了一种调试数据处理系统的方法，其中调试状态由处理器和系统电路输入，此后，当处理器核心保持在调试状态时，总线仲裁由处理器启用。

10. 发明授权

US06976110B2 Method and apparatus for reducing interrupt latency by dynamic buffer sizing 有权
标题翻译：通过动态缓冲区大小来减少中断延迟的方法和装置
公开(公告)号：US06976110B2
公开(公告)日：2005-12-13
申请号：US10740157
申请日：2003-12-18
申请人： William C. Moyer , John H. Arends
发明人： William C. Moyer , John H. Arends
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.
摘要翻译：一种用于减少数据处理系统中的中断延迟的方法，其中提供具有预定最大数量的存储位置的存储设备。数据执行电路耦合到存储设备，用于向存储设备提供数据并将数据存储在存储设备中。中断控制电路耦合到数据执行电路，其中中断控制电路中断数据执行电路。存储在存储设备中的数据被完全输出，从而具有由存储的数据的输出产生的相关联的中断延迟。存储设备的存储容量被动态地改变以最小化中断等待时间。存储装置具有基于数据处理系统的操作模式在预定的最小数量的存储位置和预定的最大数量的存储位置之间变化的利用值。

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