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1. 发明授权

US4121296A Digital signal processing arrangement 失效
标题翻译：数字信号处理装置
公开(公告)号：US4121296A
公开(公告)日：1978-10-17
申请号：US808095
申请日：1977-06-20
申请人： Wilfred Andre Maria Snijders , Nicolaas Alphonsus Maria Verhoeckx , Petrus Josephus Van Gerwen , Hendrik Arie Van Essen
发明人： Wilfred Andre Maria Snijders , Nicolaas Alphonsus Maria Verhoeckx , Petrus Josephus Van Gerwen , Hendrik Arie Van Essen
IPC分类号： H03H15/00 , G06F17/15 , H03H17/00 , H03H17/02 , H03H19/00 , H04L27/04 , G06F15/34
CPC分类号： G06F17/15 , H03H17/0227 , H03H17/0233 , H04L27/04
摘要： Digital signal processing arrangement such as a digital filter for computing output signal samples which are each equal to the sum of products of a given plurality of pairs (for example N) of input signal samples. One of the input signal samples of the pair is, for example, formed each time by a sample x(n) of a digital signal to be filtered, the other input signal sample of the pair by a filter coefficient z(n), wherein either the sample x(n) or the filter coefficient z(n) can assume only a limited number of values 0, .+-.A.sub.1, .+-.A.sub.2, . . . .+-.A.sub.M, M being much smaller than N. In the case x(n) can assume only this limited number of values, z(n) is first multiplied, owing to the x(n) belonging to the pair, by the sign of x(n) for generating a product of the form z(n). sgn [x(n)]. In-dependent of the magnitude of n(n) this product is applied to an accumulator which corresponds with this magnitude of x(n). N products have been applied to one of the M accumulators the partial sums stored therein are multiplied by the magnitude .vertline.x(n).vertline. corresponding therewith and the products obtained are added together.
摘要翻译：数字信号处理装置，例如用于计算输出信号样本的数字滤波器，每个输出信号样本各自等于给定多对（例如N个）输入信号样本的乘积之和。例如，该对的输入信号采样之一每次由要滤波的数字信号的采样x（n）形成，该对的另一个输入信号采样通过滤波器系数z（n），其中样本x（n）或滤波器系数z（n）可以仅采用有限数量的值0，+/- A1，+/- A2，。。 +/- AM，M远小于N.在x（n）可以仅假设这个有限数量的值的情况下，由于属于该对的x（n），z（n）首先乘以 x（n）的符号，用于生成形式为z（n）的乘积。 sgn [x（n）]。依赖于n（n）的大小，该乘积被施加到对应于x（n）的这个大小的累加器。已经将N个产品应用于M个累加器中的一个，其中存储的部分和乘以与其对应的幅度| x（n）|，并将获得的乘积相加。

2. 发明授权

US3997773A Interpolating digital filter with input buffer 失效
标题翻译：插入数字滤波器与输入缓冲器
公开(公告)号：US3997773A
公开(公告)日：1976-12-14
申请号：US607611
申请日：1975-08-25
申请人： Hendrik Arie Van Essen , Nicolaas Alphonsus Maria Verhoeckx , Wilfred Andre Maria Snijders
发明人： Hendrik Arie Van Essen , Nicolaas Alphonsus Maria Verhoeckx , Wilfred Andre Maria Snijders
IPC分类号： H03H17/00 , H03H17/06 , G06F7/38 , G06F15/34
CPC分类号： H03H17/0657
摘要： A non-recursive interpolating digital filter for generating, output code works, at an arbitrary rational ratio between the input and output sampling frequencies. The input code words are entered and stored in a buffer, and entered into a storage device at predetermined times determined by a controlled pulse generator.
摘要翻译：一种非递归内插数字滤波器，用于以输入和输出采样频率之间的任意合理比率产生，输出代码工作。输入的代码字被输入并存储在缓冲器中，并以由受控脉冲发生器确定的预定时间进入存储装置。

3. 发明授权

US3988607A Interpolating digital filter 失效
标题翻译：插值数字滤波器
公开(公告)号：US3988607A
公开(公告)日：1976-10-26
申请号：US607630
申请日：1975-08-25
申请人： Ludwig Desire Johan Eggermont , Hendrik Arie Van Essen , Petrus Josephus Van Gerwen , Wilfred Andre Maria Snijders
发明人： Ludwig Desire Johan Eggermont , Hendrik Arie Van Essen , Petrus Josephus Van Gerwen , Wilfred Andre Maria Snijders
IPC分类号： H03H17/00 , H03H17/06 , G06F7/38 , G06F15/34
CPC分类号： H03H17/0657 , H03H17/0621
摘要： An interpolating non-recursive digital filter in which the circulating storage device which has a periodically changing storage time, is controlled by a clock-pulse generator, and has an output circuit whereby within one input sampling period the input code words stored in the storage device are supplied a predetermined number of times to the multiplying device.
摘要翻译：具有周期性变化的存储时间的循环存储装置的内插非递归数字滤波器由时钟脉冲发生器控制，并且具有输出电路，在一个输入采样周期内存储在存储装置中的输入码字向乘法装置提供预定次数。

4. 发明授权

US3978323A Apparatus for achieving predetermined transfer characteristics 失效
标题翻译：实现预测传输特性的装置
公开(公告)号：US3978323A
公开(公告)日：1976-08-31
申请号：US565390
申请日：1975-04-07
申请人： Wolfgang Friedrich Georg Mecklenbrauker , Petrus Josephus VAN Gerwen , Wilfred Andre Maria Snijders , Theodoor Antonius Carel Maria Claasen , Hendrik Arie Van Essen
发明人： Wolfgang Friedrich Georg Mecklenbrauker , Petrus Josephus VAN Gerwen , Wilfred Andre Maria Snijders , Theodoor Antonius Carel Maria Claasen , Hendrik Arie Van Essen
IPC分类号： H03H17/02 , H03H7/01 , H03H11/04 , H03H17/06 , H04B3/04 , H04B3/06 , H04B3/14 , H04L25/03 , H04L25/48 , G06F7/38
CPC分类号： H04L25/03146 , H03H17/0236 , H03H17/06 , H04B3/04 , H03H2218/10
摘要： An apparatus for producing a predetermined transfer characteristic of information-containing signals, comprising clock means for generating a clock pulse, input means for supplying digital representations of said information-containing signals; coefficient generator means for supplying a first train of pulses of digital multiplication coefficients; delay means; digital multiplier means; and a storage device including an alternator provided with a sign reversing device and a summation device.

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