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1. 发明授权

US06862203B2 Memory with shielding effect 有权
标题翻译：内存具有屏蔽效果
公开(公告)号：US06862203B2
公开(公告)日：2005-03-01
申请号：US10658324
申请日：2003-09-10
申请人： Wen-Chieh Lee , Chang-Ting Chen
发明人： Wen-Chieh Lee , Chang-Ting Chen
IPC分类号： G11C7/18 , G11C7/02
CPC分类号： G11C7/02 , G11C7/18
摘要： A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.
摘要翻译：在本发明中公开了具有屏蔽效果的半导体存储器。存储器包括至少多个字线，一个接地线控制单元和多个存储器单元。每个存储单元包括主位线，地线，第一等效开关和第二等效开关。主位线由控制信号使能。地线和地线控制单元电连接。第一等效开关耦合到主位线和地线，并且由前一个存储器单元的控制信号控制。第二等效开关耦合到下一个存储器单元的主位线和接地线，并由下一个存储器单元的控制信号控制。

2. 发明授权

US08338969B2 Serial advanced technology attachment interface storage device 有权
标题翻译：串行高级技术附件接口存储设备
公开(公告)号：US08338969B2
公开(公告)日：2012-12-25
申请号：US12694564
申请日：2010-01-27
申请人： I-An Chen , Wen-Chieh Lee
发明人： I-An Chen , Wen-Chieh Lee
IPC分类号： H01L23/48
CPC分类号： G06K19/07732 , G06F3/0679
摘要： A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.
摘要翻译：串行高级技术附件（SATA）接口存储设备。 SATA接口存储设备可以与电气设备协同使用，并且包括基板，芯片组，SATA接口和外壳。衬底具有第一表面，对应于第一表面的第二表面和在第一表面和第二表面之间的多个连接器。芯片组设置在第一表面上。 SATA接口设置在第二表面上，并且经由一部分连接器电连接到芯片组，使得电气设备可以经由SATA接口电连接到芯片组以访问芯片组。壳体具有宽度和厚度并且限定用于接收基板，芯片组和SATA接口的接收空间，其中宽度和厚度符合微存储卡标准。

3. 发明申请

US20090104769A1 Semiconductor chip with coil element over passivation layer 有权
标题翻译：半导体芯片具有钝化层上的线圈元件
公开(公告)号：US20090104769A1
公开(公告)日：2009-04-23
申请号：US12276419
申请日：2008-11-24
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L21/283
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
摘要翻译：一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

4. 发明申请

US20070223274A1 Complex Memory Chip 审中-公开
标题翻译：复杂内存芯片
公开(公告)号：US20070223274A1
公开(公告)日：2007-09-27
申请号：US11689760
申请日：2007-03-22
申请人： Wen-Chieh Lee , Hsiang-Cheng Ho
发明人： Wen-Chieh Lee , Hsiang-Cheng Ho
IPC分类号： G11C14/00 , G11C7/10 , G11C11/34
CPC分类号： G11C5/066 , G11C5/14 , G11C11/005
摘要： A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.
摘要翻译：提供复杂的存储器芯片。复合存储器芯片包括第一引脚，第二引脚，电压发生器，闪存和静态随机存取存储器（SRAM）。第一引脚能够发送第一电压。第二引脚能够传输低于第一电压的第二电压，以便与第一电压相关联地定义工作电压。电压发生器根据第一电压产生第三电压，其中第三电压大于第一电压。闪存和SRAM在工作电压下工作。闪存根据第三电压擦除数据。

5. 发明授权

US06633999B1 Integrated circuit with on-chip data checking resources 有权
标题翻译：具有片上数据检测资源的集成电路
公开(公告)号：US06633999B1
公开(公告)日：2003-10-14
申请号：US09475329
申请日：1999-12-30
申请人： Wen-Chieh Lee
发明人： Wen-Chieh Lee
IPC分类号： G11B2100
CPC分类号： G06F11/1008 , G11C29/42
摘要： An integrated circuit with on-chip resources to support the testing of data stored on the integrated circuit includes logic to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code produced using the stored version of the data set is compared with a test code produced using a correct version of the data set, to indicate whether the correct data set was successfully stored on the device. An on-chip store holds the code produced using the correct version, and an on-chip comparator is used to produce a flag indicating the success or failure of the test. During manufacturing of the device, the memory tester simply tests the flag.
摘要翻译：具有用于支持对存储在集成电路上的数据的测试的片上资源的集成电路包括使用存储在设备上的特定数据集的数据或数据和地址的组合来计算校验码的逻辑。将使用存储的数据集的版本产生的检查码与使用正确版本的数据集产生的测试代码进行比较，以指示正确的数据集是否已成功存储在设备上。片上存储器保存使用正确版本产生的代码，并且片上比较器用于产生指示测试成功或失败的标志。在设备制造过程中，记忆体测试仪只需测试标志。

6. 发明申请

US20110233776A1 SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER 有权
标题翻译：半导体芯片与线圈元件在钝化层之间
公开(公告)号：US20110233776A1
公开(公告)日：2011-09-29
申请号：US13159147
申请日：2011-06-13
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
摘要翻译：一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

7. 发明授权

US07470927B2 Semiconductor chip with coil element over passivation layer 有权
标题翻译：半导体芯片具有钝化层上的线圈元件
公开(公告)号：US07470927B2
公开(公告)日：2008-12-30
申请号：US11434861
申请日：2006-05-17
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L31/062
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
摘要翻译：一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

8. 发明申请

US20050251689A1 Computer system for playing encrypted multimedia data and method for the same 审中-公开
标题翻译：用于播放加密多媒体数据的计算机系统和方法相同
公开(公告)号：US20050251689A1
公开(公告)日：2005-11-10
申请号：US11068746
申请日：2005-03-02
申请人： Wen-Chieh Lee , Chi-Min Liu , Tsun-Chung Yang
发明人： Wen-Chieh Lee , Chi-Min Liu , Tsun-Chung Yang
IPC分类号： H04L9/08 , G06F9/00 , G06F11/30 , G06F12/14 , H04L9/32 , H04N7/167 , H04N21/4143 , H04N21/4405 , H04N21/443
CPC分类号： H04N7/1675 , G06F2221/2107 , H04N21/4143 , H04N21/4405 , H04N21/4432
摘要： A computer system and a method for playing encrypted multimedia data are proposed. The computer system has a first operating system that heavily consumes system resources and a second operating system that slightly consumes the system resources. Via a basic input/output system (BIOS), the computer system is booted with a second operating system. The second operating system uses a multimedia-receiving unit to receive remote encrypted multimedia data and store the data into a storage unit. The second operating system uses a decrypting unit to access at least one kind of the encrypted multimedia data stored in the storage unit and the register information corresponding to the encrypted multimedia data from a first operating system for decryption. After the decrypting operation is completed, a playback unit is used to access the multimedia data that has been decrypted for perform a playback operation.
摘要翻译：提出了一种用于播放加密多媒体数据的计算机系统和方法。计算机系统具有大量消耗系统资源的第一操作系统和稍微消耗系统资源的第二操作系统。通过基本输入/输出系统（BIOS），计算机系统由第二个操作系统启动。第二操作系统使用多媒体接收单元接收远程加密多媒体数据并将数据存储到存储单元中。第二操作系统使用解密单元来访问存储在存储单元中的至少一种加密多媒体数据和来自第一操作系统的加密多媒体数据的登记信息以进行解密。在完成解密操作之后，使用重放单元访问已被解密用于执行播放操作的多媒体数据。

9. 发明申请

US20050237836A1 Refresh methods for RAM cells featuring high speed access 失效
标题翻译：具有高速访问的RAM单元的刷新方法
公开(公告)号：US20050237836A1
公开(公告)日：2005-10-27
申请号：US10829207
申请日：2004-04-22
申请人： Hong-Gee Fang , Wen-Chieh Lee , Wei-Chieh Wu , Ching-Wen Chen
发明人： Hong-Gee Fang , Wen-Chieh Lee , Wei-Chieh Wu , Ching-Wen Chen
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4061
摘要： A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.
摘要翻译：一种操作包括以行和列形成的单元阵列的存储器件的方法，所述存储器件包括提供控制信号，激活所述控制信号，所述激活的控制信号包括第一状态和第二状态，响应于所述第一状态和第二状态连续执行访问周期在一段时间内激活的控制信号的第一状态，并且在该周期的另一部分中响应于激活的控制信号的第二状态连续地执行刷新周期。

10. 发明申请

US20050040895A1 [LOW POWER CONSUMPTION CIRCUIT AND DELAY CIRCUIT THEREOF] 审中-公开
标题翻译： [低功耗电路及其延迟电路]
公开(公告)号：US20050040895A1
公开(公告)日：2005-02-24
申请号：US10710764
申请日：2004-08-02
申请人： Hong-Gee Fang , Wen-Chieh Lee , Chih-Yuan Cheng
发明人： Hong-Gee Fang , Wen-Chieh Lee , Chih-Yuan Cheng
IPC分类号： H03B5/24 , H03K3/012 , H03K3/03 , H03L7/00
CPC分类号： H03K3/0315 , H03K3/012
摘要： A low power consumption oscillation circuit and a delay circuit thereof are disclosed. The circuit comprises an enable circuit, an oscillator delay circuit and a feedback control network. The enable circuit is adapted for receiving an enable signal and performing an initial oscillation. The enable circuit outputs an initial oscillation signal according to a feedback control signal. The oscillator delay circuit is coupled to the enable circuit and is adapted for alternately generating a high and a low level oscillation signals according to the initial oscillation signal. The feedback control network is coupled to the oscillator delay circuit and is adapted for integrating the high and the low level oscillation signals to generate a feedback control signal and outputting the feedback control signal to the enable the circuit for activating next oscillation.
摘要翻译：公开了一种低功耗振荡电路及其延迟电路。该电路包括使能电路，振荡器延迟电路和反馈控制网络。使能电路适于接收使能信号并执行初始振荡。使能电路根据反馈控制信号输出初始振荡信号。振荡器延迟电路耦合到使能电路，适用于根据初始振荡信号交替产生高电平和低电平的振荡信号。反馈控制网络耦合到振荡器延迟电路，适用于对高电平和低电平振荡信号进行积分以产生反馈控制信号，并将反馈控制信号输出到启动下一个振荡电路。

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