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1. 发明授权

US06181674B2 Method and apparatus for sharing transmit shaping filters among phase shifted signals 有权
标题翻译：用于在相移信号之间共享发射整形滤波器的方法和装置
公开(公告)号：US06181674B2
公开(公告)日：2001-01-30
申请号：US09164428
申请日：1998-09-30
申请人： Weizhuang Xin , Ganning Yang , Kenneth S. Walley
发明人： Weizhuang Xin , Ganning Yang , Kenneth S. Walley
IPC分类号： H04J1100
CPC分类号： H04L25/03834 , H04L27/20
摘要： A unique system for efficiently implementing filtered, phase shifted channels is disclosed. Instead of using separate transmit shaping filters for each channel, and modulating the filtered signals with phase-shifted carrier and one might suppose, the system phase rotates the signals for each channel and modulates such phase rotated signals with a single carrier. In addition, the system decomposes the phase rotations into 90° pre-filter portions and a post-filter portion of, for example, 45°. In an 8 channel system, such as proposed in the IS-95B standard, the channels are divided into two groups and the 90° phase rotations for each group are done at the input of the transmit shaping filters. A 45° phase rotation is then done for one of the groups at the output of the transmit shaping filter. Significantly, no multiplication is required.
摘要翻译：公开了一种用于有效实施滤波的相移信道的独特系统。代替为每个通道使用单独的发送整形滤波器，并且用相移载波调制滤波信号，并且可以假设，系统相位旋转每个信道的信号并且用单载波调制这种相位旋转的信号。此外，系统将相位旋转分解为90°预过滤部分和后过滤部分，例如45°。在诸如IS-95B标准中提出的8通道系统中，通道被分成两组，每组的90°相位旋转在发送整形滤波器的输入处完成。然后，在发射整形滤波器的输出处，对于组之一进行45°相位旋转。值得注意的是，不需要乘法。

2. 发明授权

US06263027B1 Modulator and process for minimizing power consumption and communication system employing same 有权
标题翻译：用于最小化功耗的调制器和过程以及采用该功能的通信系统
公开(公告)号：US06263027B1
公开(公告)日：2001-07-17
申请号：US09161154
申请日：1998-09-25
申请人： Ganning Yang , Weizhuang Xin
发明人： Ganning Yang , Weizhuang Xin
IPC分类号： H03C300
CPC分类号： H03C3/40
摘要： A modulator is configured with a first multiplexer having a first data signal input coupled to receive the first digital baseband signal and a second data signal input coupled to receive the second digital baseband signal. The first multiplexer provides a multiplexed output signal including components of the first and second digital baseband signals. The modulator also includes a source of alternating samples of first and second carrier signals and a multiplier having a first input coupled to the output of the first multiplexer and a second input coupled to the source of carrier signal samples. The multiplier is thereby coupled to provide a digital modulated output signal. The source of alternating samples of first and second baseband signals may include a second multiplexer having a first signal input coupled to receive a first carrier signal and a second signal input coupled to receive a second carrier signal. Alternatively, the source of alternating samples of first and second baseband signals may include a memory device for storing values associated with such samples and for providing access to such values in consecutive order of occurrence of the associated samples in the baseband signals.
摘要翻译：调制器配置有第一多路复用器，其具有耦合以接收第一数字基带信号的第一数据信号输入和耦合以接收第二数字基带信号的第二数据信号输入。第一复用器提供包括第一和第二数字基带信号的分量的多路复用输出信号。调制器还包括第一和第二载波信号的交替采样的源和具有耦合到第一多路复用器的输出的第一输入和耦合到载波信号样本源的第二输入的乘法器。因此乘法器被耦合以提供数字调制输出信号。第一和第二基带信号的交替采样的源可以包括具有耦合以接收第一载波信号的第一信号输入和耦合以接收第二载波信号的第二信号输入的第二多路复用器。或者，第一和第二基带信号的交替采样的源可以包括用于存储与这些样本相关联的值的存储器装置，并且用于以基带信号中的相关样本的连续出现顺序提供对这些值的访问。

3. 发明授权

US06268818B1 Method and apparatus for improving modulation accuracy 失效
标题翻译：提高调制精度的方法和装置
公开(公告)号：US06268818B1
公开(公告)日：2001-07-31
申请号：US09103418
申请日：1998-06-24
申请人： Weizhuang Xin , Ganning Yang
发明人： Weizhuang Xin , Ganning Yang
IPC分类号： H03M182
CPC分类号： H03D7/00 , H03M1/0614 , H03M1/66
摘要： A system for digital-to-analog conversion and up-conversion (frequency multiplication) that reduces the distortion and attenuation caused by the sinc effect is described. The shape of the sinc function that gives rise to the sinc effect is altered in a manner such that the distortion produced by the sinc effect is reduced. The output of a digital-to-analog converter is provided with a return-to-zero (RTZ) output such that the digital-to-analog converter produces output pulses rather than output levels as would be expected from a conventional sample-and-hold output. The use of output pulses pushes the first null of the sinc function to a relatively higher frequency and thus the sinc function does not produce as much distortion in the harmonics of the sampled signal. Since the harmonics are less distorted, a bandpass filter or other filter can be used to extract harmonics of the sampled signal rather than the fundamental frequency. In this manner, the digital-to-analog converter and filter together provide digital-to-analog conversion and frequency multiplication (up-conversion).
摘要翻译：描述了减少由正弦效应引起的失真和衰减的数模转换和上变频（倍频）的系统。引起sinc效应的sinc函数的形状以使得由sinc效应产生的变形减小的方式改变。数模转换器的输出被提供有归零（RTZ）输出，使得数模转换器产生输出脉冲而不是输出电平，如从传统的采样 - 保持输出。输出脉冲的使用将sinc函数的第一个空值推送到相对较高的频率，因此sinc函数不会在采样信号的谐波中产生尽可能多的失真。由于谐波较小失真，所以可以使用带通滤波器或其他滤波器来提取采样信号的谐波而不是基频。以这种方式，数模转换器和滤波器一起提供数模转换和倍频（上转换）。

4. 发明授权

US08219897B2 Low complexity decoding of low density parity check codes 有权
公开(公告)号：US08219897B2
公开(公告)日：2012-07-10
申请号：US13346513
申请日：2012-01-09
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

5. 发明申请

US20090217128A1 Low complexity decoding of low density parity check codes 有权
标题翻译：低密度奇偶校验码的低复杂度解码
公开(公告)号：US20090217128A1
公开(公告)日：2009-08-27
申请号：US12288334
申请日：2008-10-17
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. Counts of the number of input weak and medium variable messages can be included in the determination of check node output messages.
摘要翻译：提供了一种用于低密度奇偶校验（LDPC）码的改进的解码器和解码方法。通过重复的消息从一组变量节点传递到一组校验节点，并从校验节点返回到变量节点进行解码。可变节点输出消息包括关于相关比特值的“最佳猜测”，以及给出对猜测（例如，弱，中等或强）的置信度的权重。校验节点输出消息具有从包括中性，弱，中等和强度的预定集合中选择的大小。如果校验节点奇偶校验被满足，则校验节点输出消息倾向于加强输入变量节点的状态，并且如果校验节点奇偶校验不满足，倾向于翻转输入变量节点中的比特。变量节点消息权重用于确定校验节点消息大小。输入的弱和中等可变消息的数量的计数可以包括在确定节点输出消息中。

6. 发明申请

US20060190797A1 Low complexity decoding of low density parity check codes 有权
公开(公告)号：US20060190797A1
公开(公告)日：2006-08-24
申请号：US11064767
申请日：2005-02-24
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess (e.g., weak, medium or strong). The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. Counts of the number of input weak and medium variable messages can be included in the determination of check node output messages.

7. 发明授权

US08095863B2 Low complexity decoding of low density parity check codes 有权
标题翻译：低密度奇偶校验码的低复杂度解码
公开(公告)号：US08095863B2
公开(公告)日：2012-01-10
申请号：US12963321
申请日：2010-12-08
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： G06F11/10
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.
摘要翻译：提供了一种用于低密度奇偶校验（LDPC）码的改进的解码器和解码方法。通过重复的消息从一组变量节点传递到一组校验节点，并从校验节点返回到变量节点进行解码。可变节点输出消息包括关于相关位值的“最佳猜测”，以及给出对猜测的置信度的权重。校验节点输出消息具有从包括中性，弱，中等和强度的预定集合中选择的大小。如果校验节点奇偶校验被满足，则校验节点输出消息倾向于加强输入变量节点的状态，并且如果校验节点奇偶校验不满足，倾向于翻转输入变量节点中的比特。变量节点消息权重用于确定校验节点消息大小。

8. 发明授权

US07856593B2 Low complexity decoding of low density parity check codes 有权
标题翻译：低密度奇偶校验码的低复杂度解码
公开(公告)号：US07856593B2
公开(公告)日：2010-12-21
申请号：US12288334
申请日：2008-10-17
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： G06F11/10
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.
摘要翻译：提供了一种用于低密度奇偶校验（LDPC）码的改进的解码器和解码方法。通过重复的消息从一组变量节点传递到一组校验节点，并从校验节点返回到变量节点进行解码。可变节点输出消息包括关于相关位值的“最佳猜测”，以及给出对猜测的置信度的权重。校验节点输出消息具有从包括中性，弱，中等和强度的预定集合中选择的大小。如果校验节点奇偶校验被满足，则校验节点输出消息倾向于加强输入变量节点的状态，并且如果校验节点奇偶校验不满足，倾向于翻转输入变量节点中的比特。变量节点消息权重用于确定校验节点消息大小。

9. 发明授权

US06707822B1 Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method 失效
标题翻译：多会话非对称数字用户线缓冲和调度设备及方法
公开(公告)号：US06707822B1
公开(公告)日：2004-03-16
申请号：US09479611
申请日：2000-01-07
申请人： Jalil Fadavi-Ardekani , Walter G. Soto , Weizhuang Xin
发明人： Jalil Fadavi-Ardekani , Walter G. Soto , Weizhuang Xin
IPC分类号： H04B138
CPC分类号： H04L25/05 , H04L1/004 , H04L5/14
摘要： A transceiver for an asymmetric communication system is provided that implements a buffering and scheduling scheme that utilizes a virtual clock signal to synchronize processing of asynchronous frame data for multiple ADSL sessions. In every virtual clock cycle, the transceiver first sequentially performs transmit-processes for each active ADSL line and then sequentially performs receive-processes for each active ADSL line. An Asynchronous Transfer Mode (ATM) Acceleratol provides the network interface to multiple ATM channels and communicates frame data to a Frame Buffer (FB). The FB may be used in a ping-pang fashion for the communication of data between the ATM accelerator and a Framer/Coder/Interleaver (FCI), which performs its namesake, among other, functions. The FCI also interfaces a Digital Signal Processing (DSP) core through an Interleave/De-Interleave Memory (IDIM). The DSP core generates the virtual clock signal, which schedules operation of the ATM accelerator and the FCI. IDIM holds DMT frames of data and may also be utilized in a ping-pang fashion. Memory is shared by multiple ADSL sessions and by the transmit and receive processes within an individual session.
摘要翻译：提供了一种用于非对称通信系统的收发器，其实现了利用虚拟时钟信号来同步多个ADSL会话的异步帧数据的处理的缓冲和调度方案。在每个虚拟时钟周期中，收发器首先对每个活动ADSL线路顺序执行发送处理，然后对每个活动的ADSL线路顺序执行接收处理。异步传输模式（ATM）Acceleratol提供到多个ATM信道的网络接口，并将帧数据传送到帧缓冲区（FB）。 FB可以以乒乓方式用于ATM加速器与执行其同名功能的成帧器/编码器/交织器（FCI）之间的数据通信。 FCI还通过Interleave / De-Interleave Memory（IDIM）将数字信号处理（DSP）核心接口。 DSP内核生成虚拟时钟信号，该时钟信号调度ATM加速器和FCI的操作。 IDIM拥有DMT数据帧，也可以以乒乓方式使用。内存由多个ADSL会话以及单个会话中的发送和接收进程共享。

10. 发明申请

US20120110408A1 LOW COMPLEXITY DECODING OF LOW DENSITY PARITY CHECK CODES 有权
标题翻译：低密度奇偶校验码的低复杂度解码
公开(公告)号：US20120110408A1
公开(公告)日：2012-05-03
申请号：US13346513
申请日：2012-01-09
申请人： Weizhuang Xin
发明人： Weizhuang Xin
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1105 , H03M13/1108
摘要： An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.
摘要翻译：提供了一种用于低密度奇偶校验（LDPC）码的改进的解码器和解码方法。通过重复的消息从一组变量节点传递到一组校验节点，并从校验节点返回到变量节点进行解码。可变节点输出消息包括关于相关位值的“最佳猜测”，以及给出对猜测的置信度的权重。校验节点输出消息具有从包括中性，弱，中等和强度的预定集合中选择的大小。如果校验节点奇偶校验被满足，则校验节点输出消息倾向于加强输入变量节点的状态，并且如果校验节点奇偶校验不满足，倾向于翻转输入变量节点中的比特。变量节点消息权重用于确定校验节点消息大小。

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