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1. 发明授权

US09553187B2 Semiconductor device and related fabrication methods 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US09553187B2
公开(公告)日：2017-01-24
申请号：US14567357
申请日：2014-12-11
申请人： Weize Chen , Richard J. De Souza , Mazhar Ul Hoque , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Mazhar Ul Hoque , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66 , H01L27/02 , H01L21/28 , H01L29/49
CPC分类号： H01L29/7835 , H01L21/28105 , H01L27/0251 , H01L29/4933 , H01L29/4983 , H01L29/66659
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a first conductivity type, a drift region and a source region each having a second conductivity type, where a channel portion of the body well region resides laterally between the source region and a first portion of the drift region that is adjacent to the channel portion. A gate structure overlies the channel portion and the adjacent portion of the drift region. A portion of the gate structure overlying the channel portion proximate the source region has the second conductivity type. Another portion of the gate structure that overlies the adjacent portion of the drift region has a different doping, and overlaps at least a portion of the channel portion, with the threshold voltage associated with the gate structure being influenced by the amount of overlap.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的主体阱区域，漂移区域和各自具有第二导电类型的源极区域，其中主体阱区域的沟道部分横向位于源极区域和源极区域的第一部分之间与沟道部分相邻的漂移区域。栅极结构覆盖了沟道部分和漂移区域的相邻部分。覆盖靠近源极区的沟道部分的栅极结构的一部分具有第二导电类型。覆盖漂移区域的相邻部分的栅极结构的另一部分具有不同的掺杂，并且与沟道部分的至少一部分重叠，与栅极结构相关联的阈值电压受重叠量的影响。

2. 发明授权

US09780558B2 Semiconductor device and related protection methods 有权
公开(公告)号：US09780558B2
公开(公告)日：2017-10-03
申请号：US14567291
申请日：2014-12-11
申请人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Mazhar Ul Hoque
发明人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Mazhar Ul Hoque
IPC分类号： H02H9/00 , H02H9/04 , H01L27/02
CPC分类号： H02H9/04 , H01L27/0251 , H02H9/046
摘要： Semiconductor devices and related electrostatic discharge (ESD) protection methods are provided. An exemplary semiconductor device includes an interface for a signal and a multi-triggered protection arrangement coupled between the interface and a reference node to initiate discharge of the signal between the interface and the reference node based on any one of a plurality of different characteristics of the signal. Discharge of the signal at the interface is initiated based on a first characteristic of the signal, and thereafter, the discharge of the signal at the interface is maintained based on another characteristic of the signal.

3. 发明申请

US20150316503A1 Differential Pair Sensing Circuit Structures 有权
标题翻译：差分传感电路结构
公开(公告)号：US20150316503A1
公开(公告)日：2015-11-05
申请号：US14265622
申请日：2014-04-30
申请人： Md M. Hoque , Patrice M. Parris , Weize Chen , Richard J. De Souza
发明人： Md M. Hoque , Patrice M. Parris , Weize Chen , Richard J. De Souza
IPC分类号： G01N27/414 , H01L29/78 , H01L29/66
CPC分类号： G01N27/4148 , H01L21/28282 , H01L27/11531 , H01L29/66 , H01L29/66409 , H01L29/78 , H01L29/788
摘要： A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.
摘要翻译：差分对检测电路（300）包括用于将参考晶体管（350）和化学敏感晶体管（351）单独编程为期望阈值电压Vt的控制栅极（306,316），以消除晶体管之间的失配，以便提高感测电路的灵敏度和/或精度，而不增加电路尺寸。

4. 发明申请

US20130270606A1 Semiconductor Device with Integrated Breakdown Protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US20130270606A1
公开(公告)日：2013-10-17
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/06 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

5. 发明授权

US08344443B2 Single poly NVM devices and arrays 有权
标题翻译：单一的NV NV设备和阵列
公开(公告)号：US08344443B2
公开(公告)日：2013-01-01
申请号：US12109736
申请日：2008-04-25
申请人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/788 , H01L27/115 , H01L21/8247
CPC分类号： H01L29/7881 , G11C16/10 , H01L27/11519 , H01L27/11521 , H01L29/42324
摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).
摘要翻译：单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213）形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

6. 发明授权

US09236472B2 Semiconductor device with integrated breakdown protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US09236472B2
公开(公告)日：2016-01-12
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

7. 发明授权

US09024380B2 Semiconductor device with floating RESURF region 有权
标题翻译：具有浮动RESURF区域的半导体器件
公开(公告)号：US09024380B2
公开(公告)日：2015-05-05
申请号：US13529589
申请日：2012-06-21
申请人： Weize Chen , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0692 , H01L29/0634 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的主体区域，具有第一导电类型，并且包括电荷载流子流过的沟道区域，半导体衬底中的漏极区域，具有第二导电类型，并与第二导电类型间隔开沿着第一横向尺寸的主体区域，具有第二导电类型的半导体衬底中的漂移区域，以及将漏极区域电耦合到沟道区域，以及在半导体衬底相邻的多个浮动缩小表面场（RESURF）区域具有第一导电类型的漂移区域，并且电荷载流子在由施加到漏极区域的电压产生的电场下漂移穿过漂移区域。多个浮动RESURF区域的相邻的浮动RESURF区域沿设备的第二横向尺寸彼此间隔开。

8. 发明申请

US20110299337A1 METHODS AND APPARATUS FOR AN ISFET 有权
标题翻译：用于ISFET的方法和装置
公开(公告)号：US20110299337A1
公开(公告)日：2011-12-08
申请号：US12794591
申请日：2010-06-04
申请人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
发明人： Patrice M. Parris , Weize Chen , Richard J. De Souza , Md M. Hoque , John M. McKenna
IPC分类号： G11C16/04 , H01L21/28 , H01L27/108
CPC分类号： G01N27/4148 , G05F1/575 , G11C16/0416 , H01L21/28035 , H01L23/5223 , H01L27/11526 , H01L27/11558 , H01L28/40 , H01L28/60 , H01L29/66825 , H01L29/788 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
摘要翻译： ISFET包括耦合到CMOS器件中的浮动栅极的控制栅极。控制栅极，例如多孔阱电容器被配置为接收偏置电压并且在控制栅极和浮置栅极之间实现俘获电荷的移动。因此，ISFET的阈值电压可以被修整到预定值，从而将修剪信息（浮置栅极中的俘获电荷的量）存储在ISFET本身内。

9. 发明申请

US20140001549A1 SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有有源器件的半导体器件和驱动器电路以及通过电阻电路互连的隔离结构及其制造方法
公开(公告)号：US20140001549A1
公开(公告)日：2014-01-02
申请号：US13671506
申请日：2012-11-07
申请人： HUBERT M. BODE , Weize Chen , Richard J. De Souza , Patrice M. Parris
发明人： HUBERT M. BODE , Weize Chen , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L27/04 , H01L21/02
CPC分类号： H01L27/04 , H01L21/02381 , H01L21/761 , H01L27/0629 , H01L27/092 , H01L29/0653 , H01L29/0847 , H01L29/0869 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66659 , H01L29/66689 , H01L29/7817 , H01L29/7835
摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).
摘要翻译：半导体器件和驱动器电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底的一部分内的有源器件，以及电阻器电路。掩埋层位于顶部衬底表面下方，并且具有第二导电类型。沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。有源器件包括主体区域，其通过具有第一导电类型的半导体衬底的一部分与隔离结构分离。电阻电路连接在隔离结构和体区之间。电阻器电路可以包括一个或多个电阻器网络，以及可选地与电阻器网络串联和/或并联的肖特基二极管和/或一个或多个PN二极管。

10. 发明授权

US07700996B2 Tunable antifuse elements 有权
标题翻译：可调谐反熔丝元件
公开(公告)号：US07700996B2
公开(公告)日：2010-04-20
申请号：US12361944
申请日：2009-01-29
申请人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
发明人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
IPC分类号： H01L29/94
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域（106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。电介质层（110）包括可调阶梯结构（127）。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

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