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1. 发明授权

US09047935B2 Read timing generation circuit 有权
标题翻译：读定时生成电路
公开(公告)号：US09047935B2
公开(公告)日：2015-06-02
申请号：US14123104
申请日：2011-11-25
申请人： Weiwei Chen , Lan Chen , Shiyang Yang
发明人： Weiwei Chen , Lan Chen , Shiyang Yang
IPC分类号： G11C7/00 , G11C7/22 , G11C8/18 , G11C8/06 , G11C7/12
CPC分类号： G11C7/222 , G11C7/12 , G11C8/06 , G11C8/18
摘要： Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit.
摘要翻译：公开了能够降低动态功耗的读定时生成电路。经过多位地址Add1，Add2，。。。，AddN通过地址变更监视部（100），生成与该地址对应的响应脉冲信号。在响应脉冲信号通过地址触发判定单元（200）之后，产生单个触发判定信号ATDPRE。单个触发判定信号ATDPRE通过ATD定时生成单元（300）和后定时生成单元（1000），从而在串行链路中形成读取定时生成电路并生成对应的读取定时。与常规读取定时生成电路相比，地址信号的每个位分别对应于执行触发，ATD控制定时输出和ATD确定处理的结构的一级，本发明大大降低了总体动态功耗电路。

2. 发明申请

US20140092697A1 READ TIMING GENERATION CIRCUIT 有权
标题翻译：阅读时序生成电路
公开(公告)号：US20140092697A1
公开(公告)日：2014-04-03
申请号：US14123104
申请日：2011-11-25
申请人： Weiwei Chen , Lan Chen , Shiyang Yang
发明人： Weiwei Chen , Lan Chen , Shiyang Yang
IPC分类号： G11C7/22 , G11C7/12
CPC分类号： G11C7/222 , G11C7/12 , G11C8/06 , G11C8/18
摘要： Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit.
摘要翻译：公开了能够降低动态功耗的读定时生成电路。经过多位地址Add1，Add2，。。。，AddN通过地址变更监视部（100），生成与该地址对应的响应脉冲信号。在响应脉冲信号通过地址触发判定单元（200）之后，产生单个触发判定信号ATDPRE。单个触发判定信号ATDPRE通过ATD定时生成单元（300）和后定时生成单元（1000），从而在串行链路中形成读取定时生成电路并生成对应的读取定时。与常规读取定时生成电路相比，地址信号的每个位分别对应于执行触发，ATD控制定时输出和ATD确定处理的结构的一级，本发明大大降低了总体动态功耗电路。

3. 发明申请

US20130135020A1 MULTI-PHASE CLOCK SIGNAL GENERATION CIRCUITS 有权
标题翻译：多相时钟信号发生电路
公开(公告)号：US20130135020A1
公开(公告)日：2013-05-30
申请号：US13574229
申请日：2011-11-30
申请人： Weiwei Chen , Lan Chen , Shuang Long
发明人： Weiwei Chen , Lan Chen , Shuang Long
IPC分类号： H03L7/00
CPC分类号： H03K5/15073 , G06F1/06 , H03K5/1508
摘要： Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. The circuit block MD1 includes two NMOS transistors, two PMOS transistors, and two delay units. The circuit block MD2 may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.
摘要翻译：公开了包括两个电路块的多相时钟信号发生电路，每个电路块包括交叉耦合结构和两个延迟单元，并且延迟单元是可调节的。电路块MD1包括两个NMOS晶体管，两个PMOS晶体管和两个延迟单元。电路块MD2可以包括两个NMOS晶体管，两个PMOS晶体管和两个延迟单元。该电路可以产生具有各自相位的时钟信号，该相位的关系相对独立于积分过程，工作电压和温度，从而允许多相电荷泵的有效效率。

4. 发明授权

US08963605B2 Multi-phase clock signal generation circuits 有权
标题翻译：多相时钟信号发生电路
公开(公告)号：US08963605B2
公开(公告)日：2015-02-24
申请号：US13574229
申请日：2011-11-30
申请人： Weiwei Chen , Lan Chen , Shuang Long
发明人： Weiwei Chen , Lan Chen , Shuang Long
IPC分类号： H03K3/00 , G06F1/04
CPC分类号： H03K5/15073 , G06F1/06 , H03K5/1508
摘要： Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.
摘要翻译：公开了包括两个电路块的多相时钟信号发生电路，每个电路块包括交叉耦合结构和两个延迟单元，并且延迟单元是可调节的。一个电路块（MD1）包括两个NMOS晶体管，两个PMOS晶体管和两个延迟单元，另一个电路块（MD2）可以包括两个NMOS晶体管，两个PMOS晶体管和两个延迟单元。该电路可以产生具有各自相位的时钟信号，该相位的关系相对独立于积分过程，工作电压和温度，从而允许多相电荷泵的有效效率。

5. 发明申请

US20120107627A1 Plating or Coating Method for Producing Metal-Ceramic Coating on a Substrate 有权
标题翻译：在基材上生产金属陶瓷涂层的电镀或涂布方法
公开(公告)号：US20120107627A1
公开(公告)日：2012-05-03
申请号：US13381487
申请日：2010-06-29
申请人： Wei Gao , Weiwei Chen
发明人： Wei Gao , Weiwei Chen
IPC分类号： B05D5/12 , C25D7/00 , B32B15/04 , C25D21/00
CPC分类号： C25D15/02 , C23C18/1637 , C23C18/1662 , C23C18/31 , C25D3/12 , C25D3/562 , C25D21/14
摘要： A method for producing a metal-ceramic composite coating with increased hardness on a substrate includes adding a sol of a ceramic phase to the plating solution or electrolyte. The sol may be added prior to and/or during the plating or coating and at a rate of sol addition controlled to be sufficiently low that nanoparticles of the ceramic phase form directly onto or at the substrate and/or that the metal-ceramic coating forms on the substrate with a predominantly crystalline structure and/or to substantially avoid formation of nanoparticles of the ceramic phase, and/or agglomeration of particles of the ceramic phase, in the plating solution or electrolyte. The ceramic phase may be a single or mixed oxide, carbide, nitride, silicate, boride of Ti, W, Si, Zr, Al, Y, Cr, Fe, Pb, Co, or a rare earth element. The coating, other than the ceramic phase may comprise Ni, Ni—P, Ni—W—P, Ni—Cu—P, Ni—B, Cu, Ag, Au, Pd.
摘要翻译：在基板上制造硬度高的金属 - 陶瓷复合涂层的方法包括将陶瓷相的溶胶添加到电镀液或电解液中。可以在电镀或涂覆之前和/或期间将溶胶加入，并且以溶胶添加速率控制为足够低，陶瓷相的纳米颗粒直接形成在基底上和/或在基底上和/或金属 - 陶瓷涂层形成在具有主要结晶结构的基底上和/或基本上避免在电镀溶液或电解质中形成陶瓷相的纳米颗粒和/或陶瓷相颗粒的聚集。陶瓷相可以是Ti，W，Si，Zr，Al，Y，Cr，Fe，Pb，Co或稀土元素的单一或混合氧化物，碳化物，氮化物，硅酸盐，硼化物。陶瓷相以外的涂层可以包含Ni，Ni-P，Ni-W-P，Ni-Cu-P，Ni-B，Cu，Ag，Au，Pd。

6. 发明授权

US08781767B2 Systems and methods for data anomaly detection 有权
标题翻译：数据异常检测系统和方法
公开(公告)号：US08781767B2
公开(公告)日：2014-07-15
申请号：US13213899
申请日：2011-08-19
申请人： Bethany Hoogs , Jason Black , Yi Zhang , Weiwei Chen , Ming Li
发明人： Bethany Hoogs , Jason Black , Yi Zhang , Weiwei Chen , Ming Li
IPC分类号： G06F19/00
CPC分类号： G06Q10/0631 , G06Q10/04 , H02J3/00 , H02J2003/003 , H02J2003/007 , Y02E60/76 , Y02P90/82 , Y04S10/54 , Y04S40/22
摘要： Systems and methods for performing data anomaly detection and/or removal are usable to accurately assess baseline power consumption. According to one embodiment of the invention, a system can be provided. The system can be operable to receive energy consumption data of a location; select, based at least in part on a collection period of the energy consumption data, an algorithm for detecting anomalies in the energy consumption data; perform the algorithm on the energy consumption data to detect the anomalies in the energy consumption data; and determine an energy consumption baseline for the location based at least in part on a result of the algorithm.
摘要翻译：用于执行数据异常检测和/或移除的系统和方法可用于准确评估基线功耗。根据本发明的一个实施例，可以提供一种系统。该系统可操作以接收位置的能量消耗数据; 至少部分地基于能量消耗数据的收集周期来选择用于检测能量消耗数据中的异常的算法; 执行能耗数据算法，检测能耗数据中的异常情况; 并且至少部分地基于所述算法的结果来确定所述位置的能量消耗基准。

7. 发明申请

US20110049587A1 Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device 有权
标题翻译：形成锗化硅层的方法，包括硅化锗层的半导体器件以及半导体器件的制造方法
公开(公告)号：US20110049587A1
公开(公告)日：2011-03-03
申请号：US12926227
申请日：2010-11-03
申请人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
发明人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/28518 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.
摘要翻译：示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。金属层可以退火以形成硅化锗层。可以使用激光尖峰退火（LSA）方法进行退火。

8. 发明申请

US20090146183A1 Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device 有权
标题翻译：形成锗化硅层的方法，包括硅化锗层的半导体器件以及半导体器件的制造方法
公开(公告)号：US20090146183A1
公开(公告)日：2009-06-11
申请号：US12078750
申请日：2008-04-04
申请人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
发明人： Chang-wook Moon , Hyun-deok Yang , Joong S. Jeon , Hwa-sung Rhee , Nae-in Lee , Weiwei Chen
IPC分类号： H01L29/78 , H01L21/20 , H01L21/335
CPC分类号： H01L29/7848 , H01L21/28518 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.
摘要翻译：示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。金属层可以退火以形成硅化锗层。可以使用激光尖峰退火（LSA）方法进行退火。

9. 外观设计

USD1049608S1 Yoga sock 有权
公开(公告)号：USD1049608S1
公开(公告)日：2024-11-05
申请号：US29936394
申请日：2024-04-08
申请人： Weiwei Chen
设计人： Weiwei Chen
摘要： FIG. 1 is a top, front and right side perspective view of a yoga sock, showing my new design;
FIG. 2 is a bottom, rear and left side perspective view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a left side elevational view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a rear elevational view thereof; and,
FIG. 8 is a front elevational view thereof.

10. 发明授权

US08942914B2 Methods and systems for managing air traffic 有权
标题翻译：管理空中交通的方法和系统
公开(公告)号：US08942914B2
公开(公告)日：2015-01-27
申请号：US13032176
申请日：2011-02-22
申请人： Rajesh Venkat Subbu , Feng Xue , Mauricio Castillo-Effen , Joel Kenneth Klooster , Joachim Karl Hochwarth , Sergio Torres , Weiwei Chen
发明人： Rajesh Venkat Subbu , Feng Xue , Mauricio Castillo-Effen , Joel Kenneth Klooster , Joachim Karl Hochwarth , Sergio Torres , Weiwei Chen
IPC分类号： G06F19/00 , G08G5/00 , G08G5/02
CPC分类号： G08G5/0013 , G08G5/0043 , G08G5/0082 , G08G5/02
摘要： Methods and system are provided for scheduling and negotiating air traffic within an airspace surrounding an airport and scheduled to land at the airport. An air traffic control (ATC) system is used to monitor the altitudes, speeds and lateral routes of aircraft. The ATC system generates a scheduled time-of-arrival (STA) at one or more meter fix points associated with the airport, the STA is stored, and data is received or inferred with the ATC system for at least a first of the aircraft, including a minimum fuel-cost speed and predicted trajectory parameters of the first aircraft based on current values of its existing trajectory parameters. Auxiliary data, including earliest and latest estimated time-of-arrival (ETAmin) and (ETAmax) at the meter fix point, STA being within/ outside ETAmin, ETAmax are generated, instructions are transmitted to the first aircraft, and the STA is updated for each aircraft stored in a queue.
摘要翻译：提供方法和系统，用于在机场周围的空域内安排和谈判空中交通，并计划在机场降落。空中交通管制（ATC）系统用于监测飞机的高度，速度和侧向航路。 ATC系统在与机场相关联的一个或多个仪表固定点处产生预定的到达时间（STA），STA被存储，并且用ATC系统接收或推断用于至少第一飞行器的数据，包括基于其现有轨迹参数的当前值的最小燃料成本速度和第一飞机的预测轨迹参数。产生辅助数据，包括在仪表固定点的最早和最近的估计到达时间（ETAmin）和（ETAmax），在ETAmin内/ ETAmin内的STA，ETAmax，指令被发送到第一飞行器，并且STA被更新对于存储在队列中的每架飞机。

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