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    • 5. 发明申请
    • Systems and Methods for Hard Decision Assisted Decoding
    • 硬判决辅助解码的系统和方法
    • US20100275096A1
    • 2010-10-28
    • US12430927
    • 2009-04-28
    • Hao ZhongShaohua YangWeijun TanChangyou XuYuan Xing Lee
    • Hao ZhongShaohua YangWeijun TanChangyou XuYuan Xing Lee
    • H03M13/00G06F11/00
    • H03M13/1111H03M13/1108H03M13/1128H03M13/3715H03M13/6331
    • Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge
    • 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。 数据检测器提供检测输出,软判决解码器将软解码算法应用于检测输出的导数,以产生软决策输出和第一硬决策输出。 该系统还包括排队缓冲器和硬判决解码器。 排队缓冲器可操作以存储软判决输出,并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。 如果软判决解码器和硬判决解码器不能收敛,则数据检测器可操作以对软决策输出的导数执行数据检测
    • 6. 发明授权
    • Systems and methods for hard decision assisted decoding
    • 硬判决辅助解码的系统和方法
    • US08443267B2
    • 2013-05-14
    • US12430927
    • 2009-04-28
    • Hao ZhongShaohua YangWeijun TanChangyou XuYuan Xing Lee
    • Hao ZhongShaohua YangWeijun TanChangyou XuYuan Xing Lee
    • G06F11/00
    • H03M13/1111H03M13/1108H03M13/1128H03M13/3715H03M13/6331
    • Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge.
    • 本发明的各种实施例提供了用于数据处理的系统和方法。 例如,公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。 数据检测器提供检测输出,软判决解码器将软解码算法应用于检测输出的导数,以产生软决策输出和第一硬决策输出。 该系统还包括排队缓冲器和硬判决解码器。 排队缓冲器可操作以存储软判决输出,并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。 如果软判决解码器和硬判决解码器不能收敛,则数据检测器可操作以对软决策输出的导数执行数据检测。
    • 7. 发明申请
    • Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    • 用于读通道的可编程准循环低密度奇偶校验(QC LDPC)编码器
    • US20100100788A1
    • 2010-04-22
    • US12288221
    • 2008-10-17
    • Shaohua YangChangyou XuRichard RauschmayerHao ZhongWeijun Tan
    • Shaohua YangChangyou XuRichard RauschmayerHao ZhongWeijun Tan
    • H03M13/27G06F11/10
    • H03M13/05G06F11/1008H03M13/116H03M13/2792
    • The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
    • 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合,并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外,编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位:p = u * GT。
    • 8. 发明授权
    • Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    • 用于读通道的可编程准循环低密度奇偶校验(QC LDPC)编码器
    • US08281214B2
    • 2012-10-02
    • US12288221
    • 2008-10-17
    • Shaohua YangChangyou XuRichard RauschmayerHao ZhongWeijun Tan
    • Shaohua YangChangyou XuRichard RauschmayerHao ZhongWeijun Tan
    • H03M13/00
    • H03M13/05G06F11/1008H03M13/116H03M13/2792
    • The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.
    • 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合,并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外,编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位:p = u * GT。
    • 9. 发明授权
    • Interleaver and de-interleaver for iterative code systems
    • 用于迭代代码系统的交织器和解交织器
    • US08205123B2
    • 2012-06-19
    • US12315601
    • 2008-12-04
    • Shaohua YangChangyou XuWeijun TanChing-Fu WuYuan Xing Lee
    • Shaohua YangChangyou XuWeijun TanChing-Fu WuYuan Xing Lee
    • H03M13/27
    • G06F12/0207H04L1/005H04L1/0057H04L1/0065
    • In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.
    • 在示例性实施例中,描述了用于迭代代码系统的偏斜交错功能。 倾斜交错功能提供了一个倾斜的行和列存储器分区以及用于重新排列从例如第一通道检测器读取的数据样本的分层结构。 诸如基于低密度奇偶校验码(LDPC)的迭代解码器的迭代解码器可以在执行数据的迭代解码之前采用去除来自交错存储器分区的数据的元素, 在将解码的样本传递到解交织器之前,将信息偏移。 解交织器在将解码的数据样本传递到例如第二信道检测器之前,根据交织器功能的反向重新排列迭代解码的数据样本。
    • 10. 发明申请
    • Interleaver and de-interleaver for iterative code systems
    • 用于迭代代码系统的交织器和解交织器
    • US20100146229A1
    • 2010-06-10
    • US12315601
    • 2008-12-04
    • Shaohua YangChangyou XuWeijun TanChing-Fu WuYuan Xing Lee
    • Shaohua YangChangyou XuWeijun TanChing-Fu WuYuan Xing Lee
    • G06F12/02G11C29/04G06F11/07
    • G06F12/0207H04L1/005H04L1/0057H04L1/0065
    • In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.
    • 在示例性实施例中,描述了用于迭代代码系统的偏斜交错功能。 倾斜交错功能提供了一个倾斜的行和列存储器分区以及用于重新排列从例如第一通道检测器读取的数据样本的分层结构。 诸如基于低密度奇偶校验码(LDPC)的迭代解码器的迭代解码器可以在执行数据的迭代解码之前采用去除来自交错存储器分区的数据的元素, 在将解码的样本传递到解交织器之前,将信息偏移。 解交织器在将解码的数据样本传递到例如第二信道检测器之前,根据交织器功能的反向重新排列迭代解码的数据样本。