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1. 发明申请

US20120038331A1 Systems and Methods of Smooth Light Load Operation in a DC/DC Converter 有权
标题翻译： DC / DC转换器平滑轻载操作的系统与方法
公开(公告)号：US20120038331A1
公开(公告)日：2012-02-16
申请号：US12854097
申请日：2010-08-10
申请人： Wenkai Wu , Weidong Zhu , Hal Chen , Xuening Li
发明人： Wenkai Wu , Weidong Zhu , Hal Chen , Xuening Li
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
摘要翻译：介绍了在DC / DC转换器中平滑轻载操作的系统和设备。所公开的系统和方法实现了平滑的不连续导通模式（DCM）/连续导通模式（CCM）转换。所公开的在DC / DC转换器中平滑轻载操作的系统和方法也可以避免在轻负载操作期间产生次谐波。在示例实施例中，上升斜坡用于控制转换器振荡器的导通时间，而下降斜坡控制OFF时间。在DCM操作期间，下降斜坡的最小值被钳位。下降斜坡的钳位确保CCM和DCM中误差放大器输出的电平基本相似，并避免由模式之间误差放大器输出的差异引起的干扰。

2. 发明授权

US09124177B2 Systems and methods of smooth light load operation in a DC/DC converter 有权
标题翻译：在DC / DC转换器中平滑轻载操作的系统和方法
公开(公告)号：US09124177B2
公开(公告)日：2015-09-01
申请号：US12854097
申请日：2010-08-10
申请人： Weidong Zhu , Xuening Li , Hal Chen , Wenkai Wu
发明人： Weidong Zhu , Xuening Li , Hal Chen , Wenkai Wu
IPC分类号： G05F1/00 , H02M3/158 , H02M1/00
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
摘要翻译：介绍了在DC / DC转换器中平滑轻载操作的系统和设备。所公开的系统和方法实现了平滑的不连续导通模式（DCM）/连续导通模式（CCM）转换。所公开的在DC / DC转换器中平滑轻载操作的系统和方法也可以避免在轻负载操作期间产生次谐波。在示例实施例中，上升斜坡用于控制转换器振荡器的导通时间，而下降斜坡控制OFF时间。在DCM操作期间，下降斜坡的最小值被钳位。下降斜坡的钳位确保CCM和DCM中误差放大器输出的电平基本相似，并避免由模式之间误差放大器输出的差异引起的干扰。

3. 发明授权

US08269570B2 Systems and methods of ripple reduction in a DC/DC converter 有权
标题翻译： DC / DC转换器中纹波降低的系统和方法
公开(公告)号：US08269570B2
公开(公告)日：2012-09-18
申请号：US12849799
申请日：2010-08-03
申请人： Xuening Li , Hal Chen , Weidong Zhu , Wenkai Wu
发明人： Xuening Li , Hal Chen , Weidong Zhu , Wenkai Wu
IPC分类号： H03K7/08 , G05F1/62 , G05F1/00
CPC分类号： H03K5/1252
摘要： Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.
摘要翻译：介绍了DC / DC转换器中纹波降低的系统和器件。所公开的系统和方法使得不连续导通模式（DCM）操作中的纹波降低。在DCM中，电感电流峰峰值纹波可能会根据负载电流而减小。为了实现电感峰值电流纹波的降低，使用数字计数器对连续PWM脉冲之间的时间进行计数。计数器的数字输出用于控制脉宽调制。随着计数器的数字输出增加，PWM导通时间减少。由于PWM模式下的负载要求PWM脉冲，所以峰值电感纹波由计数器调制，或由负载电流调制。

4. 发明申请

US20120032748A1 Systems and Methods of Ripple Reduction in a DC/DC Converter 有权
标题翻译： DC / DC转换器中波纹减少的系统和方法
公开(公告)号：US20120032748A1
公开(公告)日：2012-02-09
申请号：US12849799
申请日：2010-08-03
申请人： Xuening Li , Hal Chen , Weidong Zhu , Wenkai Wu
发明人： Xuening Li , Hal Chen , Weidong Zhu , Wenkai Wu
IPC分类号： H03K7/08 , G05F1/10 , H03K5/12
CPC分类号： H03K5/1252
摘要： Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current.
摘要翻译：介绍了DC / DC转换器中纹波降低的系统和器件。所公开的系统和方法使得不连续导通模式（DCM）操作中的纹波降低。在DCM中，电感电流峰峰值纹波可能会根据负载电流而减小。为了实现电感峰值电流纹波的降低，使用数字计数器对连续PWM脉冲之间的时间进行计数。计数器的数字输出用于控制脉宽调制。随着计数器的数字输出增加，PWM导通时间减小。由于PWM模式下的负载要求PWM脉冲，所以峰值电感纹波由计数器调制，或由负载电流调制。

5. 发明申请

US20230010611A1 FREQUENCY LOCK LOOP FOR CONSTANT SWITCHING FREQUENCY OF DC-DC CONVERTERS 有权
公开(公告)号：US20230010611A1
公开(公告)日：2023-01-12
申请号：US17305543
申请日：2021-07-09
申请人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
发明人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
IPC分类号： H02M3/04 , H03L7/08
摘要： A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

6. 发明授权

US11716024B2 Deadtime control scheme for improving buck converter light load efficiency 有权
公开(公告)号：US11716024B2
公开(公告)日：2023-08-01
申请号：US17646415
申请日：2021-12-29
申请人： Jialun Du , Jiwei Fan , Hal Chen
发明人： Jialun Du , Jiwei Fan , Hal Chen
IPC分类号： H02M3/158 , H02M1/00 , H05B45/375
CPC分类号： H02M3/158 , H02M1/0009 , H05B45/375
摘要： A deadtime control scheme for improving buck converter light load efficiency.

7. 发明授权

US11646651B2 Ramp generator for a constant on-time DC-DC converter 有权
公开(公告)号：US11646651B2
公开(公告)日：2023-05-09
申请号：US17305541
申请日：2021-07-09
申请人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
发明人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
IPC分类号： H02M1/14 , H02M3/158 , H02M1/08 , H02M1/44 , H02M1/15
CPC分类号： H02M1/143 , H02M1/08 , H02M3/158 , H02M1/14 , H02M1/15 , H02M1/44
摘要： A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.

8. 发明公开

US20230208298A1 DEADTIME CONTROL SCHEME FOR IMPROVING BUCK CONVERTER LIGHT LOAD EFFICIENCY 审中-公开
公开(公告)号：US20230208298A1
公开(公告)日：2023-06-29
申请号：US17646415
申请日：2021-12-29
申请人： Jialun Du , Jiwei Fan , Hal Chen
发明人： Jialun Du , Jiwei Fan , Hal Chen
IPC分类号： H02M3/158 , H02M1/00 , H05B45/375
CPC分类号： H02M3/158 , H02M1/0009 , H02M1/0058 , H05B45/375
摘要： A deadtime control scheme for improving buck converter light load efficiency.

9. 发明申请

US20230012123A1 RAMP GENERATOR FOR A CONSTANT ON-TIME DC-DC CONVERTER 有权
公开(公告)号：US20230012123A1
公开(公告)日：2023-01-12
申请号：US17305541
申请日：2021-07-09
申请人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
发明人： Jiwei Fan , Yingqian Ma , Jingyuan Chen , Hal Chen , Jialun Du
IPC分类号： H02M1/14 , H02M1/08 , H02M3/158
摘要： A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.

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