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1. 发明申请

US20070255997A1 Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance 失效
标题翻译：多线并行段扫描模拟芯片元件性能
公开(公告)号：US20070255997A1
公开(公告)日：2007-11-01
申请号：US11754941
申请日：2007-05-29
申请人： Wei-Yi Xiao , Dean Bair , Thomas Ruane , William Lewis
发明人： Wei-Yi Xiao , Dean Bair , Thomas Ruane , William Lewis
IPC分类号： H03M13/00
CPC分类号： G06F17/5022
摘要： A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
摘要翻译：基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品。该方法，系统和程序产品停止模拟测试用例的正常功能，启动扫描时钟，在初始时刻记录扫描环数据的第一个“快照”。然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。比较“快照”，如果“快照”都相同，则功能扫描成功。但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

2. 发明授权

US07509552B2 Multi-thread parallel segment scan simulation of chip element performance 失效
标题翻译：多线程并行段扫描模拟芯片元件性能
公开(公告)号：US07509552B2
公开(公告)日：2009-03-24
申请号：US11040140
申请日：2005-01-21
申请人： Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
发明人： Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
IPC分类号： G01R31/28 , G06F7/02
CPC分类号： G06F17/5022
摘要： A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
摘要翻译：基于微处理器底层硬件设计的微处理器仿真方法，可以在初始时间停止模拟测试仪的正常功能，启动扫描时钟，并记录扫描环数据的第一个“快照”。然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。比较“快照”，如果“快照”都相同，则功能扫描成功。但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

3. 发明申请

US20060168497A1 Multi-thread parallel segment scan simulation of chip element performance 失效
标题翻译：多线程并行段扫描模拟芯片元件性能
公开(公告)号：US20060168497A1
公开(公告)日：2006-07-27
申请号：US11040140
申请日：2005-01-21
申请人： Wei-Yi Xiao , Dean Blair , Thomas Ruane , William Lewis
发明人： Wei-Yi Xiao , Dean Blair , Thomas Ruane , William Lewis
IPC分类号： H03M13/00
CPC分类号： G06F17/5022
摘要： A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
摘要翻译：基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品。该方法，系统和程序产品停止模拟测试用例的正常功能，启动扫描时钟，在初始时刻记录扫描环数据的第一个“快照”。然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。比较“快照”，如果“快照”都相同，则功能扫描成功。但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

4. 发明授权

US07559002B2 Multi-thread parallel segment scan simulation of chip element performance 失效
标题翻译：多线程并行段扫描模拟芯片元件性能
公开(公告)号：US07559002B2
公开(公告)日：2009-07-07
申请号：US11754941
申请日：2007-05-29
申请人： Wei-Yi Xiao , Dean Gilbert Bair , Thomas Ruane , William Lewis
发明人： Wei-Yi Xiao , Dean Gilbert Bair , Thomas Ruane , William Lewis
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F17/5022
摘要： A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
摘要翻译：基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品可以停止模拟测试用例的正常功能，启动扫描时钟，并将扫描环数据的第一个“快照”记录在最初的时间。然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。比较“快照”，如果“快照”都相同，则功能扫描成功。但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

5. 发明申请

US20050251379A1 Method, system and computer program product for register management in a simulation environment 失效
标题翻译：方法，系统和计算机程序产品，用于模拟环境中的注册管理
公开(公告)号：US20050251379A1
公开(公告)日：2005-11-10
申请号：US10835324
申请日：2004-04-29
申请人： William Lewis , Wei-Yi Xiao
发明人： William Lewis , Wei-Yi Xiao
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40 , G06F11/26 , G06F17/50
CPC分类号： G06F17/5022
摘要： A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.
摘要翻译：一种在模拟环境中的寄存器管理方法，包括从指令单元解码流水线接收指令。如果指令是AGI指令，则在仿真环境中执行地址生成互锁（AGI）功能。执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。如果指令是早期AGI指令，则在仿真环境中执行早期AGI功能。执行早期AGI功能可以响应寄存器池和指令。

6. 发明申请

US20060180440A1 Conveyor belts with thin film sensor-activating coating 失效
标题翻译：输送带带薄膜传感器激活涂层
公开(公告)号：US20060180440A1
公开(公告)日：2006-08-17
申请号：US11057004
申请日：2005-02-11
申请人： William Lewis , William Lewis , Lambert Terpstra , Barton Lewis
发明人： William Lewis , William Lewis , Lambert Terpstra , Barton Lewis
IPC分类号： B65G43/00
CPC分类号： G09F19/22
摘要： A conveyor belt device wherein a detectable coating, such as in the form of a thin film, overlies selected portions of a conveyor belt substrate surface. Suitable detectable coatings include materials that are inductive, conductive, magnetic, reflective, fluorescent and color-indicating or a combination thereof. Also disclosed are associated or corresponding conveyor belt assemblies and methods of making.
摘要翻译：一种输送带装置，其中诸如薄膜形式的可检测涂层覆盖在输送带基材表面的选定部分上。合适的可检测涂层包括感应，导电，磁性，反射，荧光和颜色指示的材料或其组合。还公开了相关联或相应的传送带组件和制造方法。

7. 发明授权

US11802392B2 Coupler guard system 有权
公开(公告)号：US11802392B2
公开(公告)日：2023-10-31
申请号：US17223535
申请日：2021-04-06
申请人： William Lewis
发明人： William Lewis
IPC分类号： E02F9/22 , F16L57/00 , E02F3/36 , F16L37/56
CPC分类号： E02F9/2275 , E02F3/3654 , F16L57/005 , F16L37/56
摘要： A coupler guard configured to protect an auxiliary coupler assembly from side impacts in the rough use environment of a loader. The coupler guard comprises an encasement and a side plate. The loader comprises the auxiliary coupler assembly and a hinge extension. The encasement wraps around a top portion and interior side of the auxiliary coupler assembly. The side plate attaches to a portion of the encasement and protect an exterior side portion of the auxiliary coupler assembly. A screw assemblies selectively attaches the encasement to the side plate. A ring attaches to a portion of the side plate. The ring selectively wraps around a portion of the hinge extension of the loader. A ring screw assembly selectively holds the ring and the rest of the coupler guard to the hinge extension. An edge trim selectively sits on top of a portion of a first arm.

8. 外观设计

USD783729S1 Angle compatible block 有权
公开(公告)号：USD783729S1
公开(公告)日：2017-04-11
申请号：US29497643
申请日：2014-07-25
申请人： Debra Sterling Glasband , William Lewis , Clinton Cope
设计人： Debra Sterling Glasband , William Lewis , Clinton Cope

9. 外观设计

USD722374S1 Body for a portable heater 有权
公开(公告)号：USD722374S1
公开(公告)日：2015-02-10
申请号：US29442490
申请日：2013-03-13
申请人： William Lewis
设计人： William Lewis

10. 发明授权

US08799554B1 Methods and system for swapping memory in a virtual machine environment 有权
标题翻译：在虚拟机环境中交换内存的方法和系统
公开(公告)号：US08799554B1
公开(公告)日：2014-08-05
申请号：US12913707
申请日：2010-10-27
申请人： Pradeep Vincent , William Lewis
发明人： Pradeep Vincent , William Lewis
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F9/5016 , G06F8/4434 , G06F9/45558 , G06F12/08 , G06F12/109 , G06F2009/45583 , G06F2209/503 , G06F2212/1016 , G06F2212/152 , G06F2212/656 , G06F2212/657
摘要： In this disclosure, techniques are described for more efficiently sharing resources across multiple virtual machine instances. For example, techniques are disclosed for allowing additional virtual machine instances to be supported by a single computing system by more efficiently allocating memory to virtual machine instances by providing page swapping in a virtualized environment and/or predictive page swapping. In one embodiment, a virtual memory manager swaps pages predicatively in and/or out of a paging pool based on information from a central processing unit (“CPU”) scheduler. In one embodiment, the CPU scheduler provides scheduling information for virtual machine instances to the virtual memory manager, where the scheduling information allows the virtual memory manager to determine when a virtual machine is scheduled to become active or inactive. The virtual memory manager can then swap-in or swap-out memory pages.
摘要翻译：在本公开中，描述了用于在多个虚拟机实例之间更有效地共享资源的技术。例如，公开了通过在虚拟化环境中提供页面交换和/或预测页面交换来通过更有效地将存储器分配给虚拟机实例来允许由单个计算系统支持附加虚拟机实例的技术。在一个实施例中，虚拟存储器管理器基于来自中央处理单元（“CPU”）调度器的信息，在寻呼池内和/或之外交换页面。在一个实施例中，CPU调度器向虚拟存储器管理器提供用于虚拟机实例的调度信息，其中调度信息允许虚拟存储器管理器确定虚拟机何时被调度为活动或不活动。然后，虚拟内存管理器可以交换或交换内存页面。

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