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1. 发明授权

US07559002B2 Multi-thread parallel segment scan simulation of chip element performance 失效
标题翻译：多线程并行段扫描模拟芯片元件性能
公开(公告)号：US07559002B2
公开(公告)日：2009-07-07
申请号：US11754941
申请日：2007-05-29
申请人： Wei-Yi Xiao , Dean Gilbert Bair , Thomas Ruane , William Lewis
发明人： Wei-Yi Xiao , Dean Gilbert Bair , Thomas Ruane , William Lewis
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F17/5022
摘要： A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
摘要翻译：基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品可以停止模拟测试用例的正常功能，启动扫描时钟，并将扫描环数据的第一个“快照”记录在最初的时间。然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。比较“快照”，如果“快照”都相同，则功能扫描成功。但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

2. 发明授权

US07089518B2 Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks 失效
标题翻译：用于在具有多个时钟的系统中对异步时钟建模行为的方法和程序产品
公开(公告)号：US07089518B2
公开(公告)日：2006-08-08
申请号：US10841729
申请日：2004-05-08
申请人： Dean Gilbert Bair , Edward James Kaminski, Jr. , Bradley Sterling Nelson
发明人： Dean Gilbert Bair , Edward James Kaminski, Jr. , Bradley Sterling Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/62
摘要： Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at the boundary between the two independently clocked subsystems with a behavior model, said behavioral model comprising data receiver time delays.
摘要翻译：用于分析异步计时系统的方法和程序产品。被分析的系统具有独立的时钟子系统，其间具有时钟边界。该模型识别两个独立时钟子系统之间的边界，并识别两个独立时钟子系统之间边界的行为。以及使用行为模型在两个独立计时的子系统之间的边界处对锁存器建模，所述行为模型包括数据接收器时间延迟。

3. 发明授权

US5745386A Timing diagram method for inputting logic design parameters to build a testcase for the logic diagram 失效
标题翻译：用于输入逻辑设计参数以构建逻辑图的测试用例的时序图方法
公开(公告)号：US5745386A
公开(公告)日：1998-04-28
申请号：US533128
申请日：1995-09-25
申请人： Bruce Wile , Dean Gilbert Bair , Edward James Kaminski, Jr.
发明人： Bruce Wile , Dean Gilbert Bair , Edward James Kaminski, Jr.
IPC分类号： G01R31/317 , G06F11/26 , G06F17/50 , G06F15/62
CPC分类号： G06F17/5022 , G01R31/31704 , G06F11/261
摘要： A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.
摘要翻译： A.系统（即，工具集）在逻辑设计级别提供逻辑验证，其中从设计的外部刺激从遵循所测试的逻辑设计的接口协议的一系列广义时序图导出。时序图编辑器提供图形用户界面，允许逻辑设计者以包含接口规范排列的一般时序图格式描述他或她的逻辑。时序图编辑器的输出是描述逻辑接口的文件; 该文件可以包含描述不同接口交互的多个时序图。合适的模拟驱动程序读取由时序图编辑器创建的文件，了解其中描述的接口，并使用模拟随机化算法来驱动具有时序图中描述的接口的合法场景的接口。

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