会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • Defocus calibration module for light-sensing system and method thereof
    • 用于光感测系统的散焦校准模块及其方法
    • US20110243541A1
    • 2011-10-06
    • US12818112
    • 2010-06-17
    • Wei-Chung WangHui-Hsuan Chen
    • Wei-Chung WangHui-Hsuan Chen
    • G03B13/00
    • G03B3/00G03B13/00H04N17/002
    • A defocus calibration module is applied in a light-sensing system utilized for sensing a measured object for generating a sensed image. The light-sensing system comprises a light-emitting component, a focusing component, and an image sensor. The light-emitting component emits a detecting light to the measured object so that the measured object generates a reflecting light. The focusing component focuses the reflecting light to the image sensor. The image sensor generates the sensed image according to the reflecting light. The defocus calibration module has a calibrating object for blocking a part of the detecting light and the reflecting light for forming images at a first and a second calibration imaging locations in the sensed image. In this way, the defocus calibration module calculates a defocus parameter representing the defocus level of the light-sensing system according to the first and the second calibration imaging locations, and accordingly calibrates the sensed image.
    • 散焦校准模块应用于用于感测测量对象以产生感测图像的光感测系统中。 光感测系统包括发光部件,聚焦部件和图像传感器。 发光部件向测量对象发射检测光,使得被测物体产生反射光。 聚焦组件将反射光聚焦到图像传感器。 图像传感器根据反射光生成感测图像。 散焦校准模块具有用于阻挡检测光的一部分的校准对象和用于在感测图像中的第一和第二校准成像位置处形成图像的反射光。 以这种方式,散焦校准模块根据第一和第二校准成像位置计算表示光感测系统的散焦水平的散焦参数,并因此校准感测图像。
    • 9. 发明申请
    • Three-dimensional package and method of making the same
    • 三维包装及其制作方法
    • US20070172986A1
    • 2007-07-26
    • US11645177
    • 2006-12-26
    • Min-Lung HuangWei-Chung WangPo-Jen ChengKuo-Chung YeeChing-Huei SuJian-Wen LoChian-Chi Lin
    • Min-Lung HuangWei-Chung WangPo-Jen ChengKuo-Chung YeeChing-Huei SuJian-Wen LoChian-Chi Lin
    • H01L21/00
    • H01L25/0657H01L21/76898H01L25/50H01L2224/48145H01L2225/06506H01L2225/06524H01L2225/06541H01L2924/01019H01L2924/01078H01L2924/00012
    • The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package structure comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first metal, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, a second metal and a second space. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. The second wafer has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The lower end of the second conductive layer extends below the surface of the second wafer and contacts the upper end of the first solder. The second metal is disposed in the second hole and is electrically connected to the second pad via the second conductive layer. The second space is disposed on the second metal in the second hole.
    • 本发明涉及三维包装及其制造方法。 三维封装结构包括第一晶片,至少一个第一孔,第一隔离层,第一导电层,第一金属,第一焊料,第二晶片,至少一个第二孔,第二隔离层, 第二导电层,第二金属和第二空间。 第一晶片具有至少一个第一焊盘和暴露第一焊盘的第一保护层。 第一个孔穿透第一个晶片。 第一隔离层设置在第一孔的侧壁上。 第一导电层的下端延伸到第一晶片的表面下方。 第一金属设置在第一孔中,并且经由第一导电层电连接到第一焊盘。 第一焊料设置在第一孔中的第一金属上,其中第一焊料的熔点低于第一焊料的熔点。 第二晶片具有至少一个第二焊盘和暴露第二焊盘的第二保护层。 第二孔穿透第二晶片。 第二隔离层设置在第二孔的侧壁上。 第二导电层的下端延伸到第二晶片的表面下方并接触第一焊料的上端。 第二金属设置在第二孔中,并通过第二导电层与第二焊盘电连接。 第二空间设置在第二孔中的第二金属上。
    • 10. 发明申请
    • Three-dimensional package and method of making the same
    • 三维包装及其制作方法
    • US20070172985A1
    • 2007-07-26
    • US11645042
    • 2006-12-26
    • Min-Lung HuangWei-Chung WangPo-Jen ChengKuo-Chung YeeChing-Huei SuJian-Wen LoChain-Chi Lin
    • Min-Lung HuangWei-Chung WangPo-Jen ChengKuo-Chung YeeChing-Huei SuJian-Wen LoChain-Chi Lin
    • H01L21/00
    • H01L25/0657H01L21/76898H01L25/50H01L2224/48145H01L2225/06506H01L2225/06524H01L2225/06541H01L2924/01019H01L2924/01078H01L2924/00012
    • The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a metal; (g) removing the dry film, and patterning the conductive layer; (h) removing a part of the metal in the blind hole to form a space; (i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) forming a solder on the lower end of the conductive layer, wherein the melting point of the solder is lower than that of the metal; (k) stacking a plurality of the wafers, and performing a reflow process; and (l) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
    • 本发明涉及三维包装及其制造方法。 该方法包括:(a)提供晶片; (b)在所述晶片中形成至少一个盲孔; (c)在盲孔的侧壁上形成隔离层; (d)在隔离层上形成导电层; (e)在导电层上形成干膜; (f)用金属填充盲孔; (g)去除干膜,图案化导电层; (h)去除盲孔中的金属的一部分以形成空间; (i)去除所述晶片的所述第二表面的一部分和所述隔离层的一部分,以暴露所述导电层的一部分; (j)在导电层的下端形成焊料,其中焊料的熔点低于金属的熔点; (k)堆叠多个晶片,并进行回流处理; 和(l)切割堆叠的晶片,以便形成多个三维封装。 因此,导电层的下端和其上的焊料被“插入”到下晶片的空间中,以增强导电层和焊料之间的接合,并且有效地降低了三层结构的整体高度, 加入后立体包装。