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1. 发明授权

US06525381B1 Semiconductor-on-insulator body-source contact using shallow-doped source, and method 有权
标题翻译：使用浅掺杂源的半导体绝缘体体源接触及其方法
公开(公告)号：US06525381B1
公开(公告)日：2003-02-25
申请号：US09541127
申请日：2000-03-31
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L2976
CPC分类号： H01L29/66772 , H01L29/41733 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.
摘要翻译：半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。半导体区域的导电区域与源极区域和体区域重叠并电耦合。源极和体区的电耦合减少了半导体器件中的浮体效应。构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域漏极区域。

2. 发明授权

US06373103B1 Semiconductor-on-insulator body-source contact using additional drain-side spacer, and method 有权
标题翻译：使用附加的漏极侧隔离物的绝缘体上的半导体体源接触及其方法
公开(公告)号：US06373103B1
公开(公告)日：2002-04-16
申请号：US09541124
申请日：2000-03-31
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L2701
CPC分类号： H01L29/78624 , H01L29/41733 , H01L29/78612
摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.
摘要翻译：半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。半导体区域的导电区域与源极区域和体区域重叠并电耦合。源极和体区的电耦合减少了半导体器件中的浮体效应。构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域漏极区域。

3. 发明授权

US06790750B1 Semiconductor-on-insulator body-source contact and method 有权
标题翻译：绝缘体上的绝缘体源极接触和方法
公开(公告)号：US06790750B1
公开(公告)日：2004-09-14
申请号：US10163676
申请日：2002-06-06
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L21425
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.
摘要翻译：半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。半导体区域的导电区域与源极区域和体区域重叠并电耦合。源极和体区的电耦合减少了半导体器件中的浮体效应。构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域漏极区域。

4. 发明授权

US6153534A Method for fabricating a dual material gate of a short channel field effect transistor 失效
标题翻译：短沟道场效应晶体管的双材料栅极的制造方法
公开(公告)号：US6153534A
公开(公告)日：2000-11-28
申请号：US361826
申请日：1999-07-27
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L29/49 , H01L21/302 , H01L21/461
CPC分类号： H01L29/66659 , H01L21/28105 , H01L21/2815 , H01L29/1054 , H01L29/4983 , H01L21/2807
摘要： A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention includes a step of forming a first material gate portion on a gate dielectric. The first material gate portion has a source side and a drain side, and an aspect of the present invention further includes the step of depositing a spacer dielectric layer on the source side and the drain side of the first material gate portion. An aspect of the present invention also includes the step of implanting heavy ions into the spacer dielectric layer at an angle such that the spacer dielectric layer at the drain side of the first material gate portion is substantially not implanted with the heavy ions. The spacer dielectric layer is then selectively etched such that any portion of the spacer dielectric layer that is implanted with the heavy ions is etched. Thus, the spacer dielectric layer on the drain side of the first material gate portion is not etched, but the spacer dielectric layer on the source side of the first material gate portion is etched. In addition, an aspect of the present invention includes a step of selectively growing a second material gate portion from the first material gate portion that is exposed on the source side of the first material gate portion. In this manner, the dual material gate of the field effect transistor is comprised of the first material gate portion toward the drain of the field effect transistor and the second material gate portion toward the source of the field effect transistor.
摘要翻译：对于具有亚微米和纳米尺寸的短沟道长度的场效应晶体管有效地制造双材料栅极，使得不利的短沟道效应最小化。通常，本发明的方法包括在栅极电介质上形成第一材料栅极部分的步骤。第一材料栅极部分具有源极侧和漏极侧，并且本发明的一个方面还包括在第一材料栅极部分的源极侧和漏极侧上沉积间隔电介质层的步骤。本发明的一个方面还包括以一定角度将重离子注入到间隔电介质层中的步骤，使得第一材料栅极部分的漏极侧的间隔电介质层基本上不被重离子注入。然后选择性地蚀刻间隔电介质层，使得蚀刻注入了重离子的间隔电介质层的任何部分。因此，第一材料栅极部分的漏极侧的间隔物电介质层未被蚀刻，而是蚀刻第一材料栅极部分的源极侧的间隔物电介质层。此外，本发明的一个方面包括从第一材料栅极部分选择性地生长第二材料栅极部分的步骤，该第一材料栅极部分暴露在第一材料栅极部分的源极侧。以这种方式，场效应晶体管的双材料栅极包括朝向场效应晶体管的漏极的第一材料栅极部分和朝向场效应晶体管的源极的第二材料栅极部分。

5. 发明授权

US06441434B1 Semiconductor-on-insulator body-source contact and method 有权
标题翻译：绝缘体上的绝缘体源极接触和方法
公开(公告)号：US06441434B1
公开(公告)日：2002-08-27
申请号：US09541126
申请日：2000-03-31
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78612 , H01L29/78624
摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.
摘要翻译：半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。半导体区域的导电区域与源极区域和体区域重叠并电耦合。源极和体区的电耦合减少了半导体器件中的浮体效应。构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域漏极区域。

6. 发明授权

US06169302A Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor 失效
标题翻译：确定场效应晶体管的栅极和漏极/源局部互连之间的寄生电容
公开(公告)号：US06169302A
公开(公告)日：2001-01-02
申请号：US09361698
申请日：1999-07-27
申请人： Wei Long , Qi Xiang , Yowjuang W. Liu
发明人： Wei Long , Qi Xiang , Yowjuang W. Liu
IPC分类号： H01L2358
CPC分类号： H01L22/34 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The present invention accurately determines a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and determines a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor. A virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor includes a virtual drain local interconnect, a virtual source local interconnect, and a virtual conductive gate region fabricated on the dielectric with a respective size and positions relative to each other that are substantially the same as that of the drain and source local interconnects and the gate, respectively, of the real field effect transistor. In this manner, the first parasitic capacitance component between the conductive gate region of the real field effect transistor to the drain local interconnect of the real field effect transistor is a first capacitance measured between the virtual conductive gate region and the virtual drain local interconnect of the virtual field effect transistor of the present invention. Similarly, the second parasitic capacitance component between the conductive gate region of the real field effect transistor to the source local interconnect of the real field effect transistor is a second capacitance measured between the virtual conductive gate region and the virtual source local interconnect of the virtual field effect transistor of the present invention.
摘要翻译：本发明精确地确定实际场效应晶体管的导电栅极与漏极局部互连之间的第一寄生电容分量，并且确定导电栅区与实场效应晶体管的源局部互连之间的第二寄生电容分量。在电介质上制造虚拟场效应晶体管，以便确定真实场效应晶体管的栅极和漏极或源局部互连之间的寄生电容分量。虚拟场效应晶体管包括虚拟漏极局部互连，虚拟源局部互连和在电介质上制造的虚拟导电栅极区域，该虚拟导电栅极区域具有与漏极和源极基本上相同的尺寸和位置分别是实际场效应晶体管的局部互连和栅极。以这种方式，实际场效应晶体管的导电栅极区域与实场效应晶体管的漏极局部互连之间的第一寄生电容分量是在虚拟导电栅极区域和虚拟漏极局部互连之间测量的第一电容虚拟场效应晶体管。类似地，实场效应晶体管的导电栅极区域与实场效应晶体管的源局部互连之间的第二寄生电容分量是在虚拟导电栅极区域和虚拟场虚拟源局部互连之间测量的第二电容效应晶体管。

7. 发明授权

US06420770B1 STI (Shallow Trench Isolation) structures for minimizing leakage current through drain and source silicides 有权
标题翻译： STI（浅沟槽隔离）结构，用于通过漏极和源极硅化物最小化漏电流
公开(公告)号：US06420770B1
公开(公告)日：2002-07-16
申请号：US09882244
申请日：2001-06-15
申请人： Qi Xiang , Wei Long , Ming-Ren Lin
发明人： Qi Xiang , Wei Long , Ming-Ren Lin
IPC分类号： H01L2900
CPC分类号： H01L29/665 , H01L21/76224
摘要： STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.
摘要翻译：制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为最小化。

8. 发明授权

US06437404B1 Semiconductor-on-insulator transistor with recessed source and drain 有权
标题翻译：具有凹陷源极和漏极的绝缘体上半导体晶体管
公开(公告)号：US06437404B1
公开(公告)日：2002-08-20
申请号：US09636239
申请日：2000-08-10
申请人： Qi Xiang , Wei Long , Ming-Ren Lin
发明人： Qi Xiang , Wei Long , Ming-Ren Lin
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L21/26533 , H01L21/28079 , H01L29/6653 , H01L29/66545 , H01L29/66772 , H01L29/78603
摘要： A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.
摘要翻译：完全耗尽的绝缘体上半导体（SOI）晶体管器件具有SOI衬底，其具有相对于衬底的顶表面具有不均匀深度的掩埋绝缘体层，所述掩埋绝缘体层具有靠近顶表面的较浅部分比层的深部分。栅极形成在绝缘体层的顶表面和浅部之间的薄半导体层上。源极和漏极区域形成在栅极的任一侧上，源极和漏极区域分别位于掩埋绝缘体层的深部之一的顶部。源极和漏极区域因此具有比薄的半导体层更大的厚度。形成在源区和漏区的厚硅化物区具有低寄生电阻。制造晶体管器件的方法包括在SOI衬底上形成虚拟栅极结构，并且使用虚拟栅极结构来控制注入的深度以形成不均匀深度的掩埋绝缘体层。

9. 发明授权

US06255219B1 Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel 有权
标题翻译：制造具有横向不对称通道的高性能亚微米MOSFET的方法
公开(公告)号：US06255219B1
公开(公告)日：2001-07-03
申请号：US09391303
申请日：1999-09-07
申请人： Qi Xiang , Wei Long
发明人： Qi Xiang , Wei Long
IPC分类号： H01L2100
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; and performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, wherein the spacer facilitates formation of a lateral asymmetric channel. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area. A lateral asymmetric channel is thus formed, and the speed of the submicron MOSFET is increased.
摘要翻译：本发明提供一种制造亚微米金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括在基板上设置栅极，该基板具有源极侧和漏极侧，漏极侧具有间隔区域; 在间隔区域形成间隔物; 以及在所述源极侧和所述漏极侧执行光晕注入，其中所述间隔物防止在所述间隔区域中注入，其中所述间隔物有利于形成横向不对称通道。在优选实施例中，通过在栅极和衬底上沉积氧化物层，然后避免氧化物层在间隔区域中的氮注入，同时在氧化物层的其余部分中注入氮而形成间隔物。注入氮的氧化物和未注入氮的氧化物的蚀刻速率的差异允许选择性蚀刻氧化物层，导致间隔物在间隔区域中。因此形成横向不对称沟道，并且亚微米MOSFET的速度增加。

10. 发明授权

US06168999A Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain 有权
标题翻译：制造具有横向非对称沟道和轻掺杂漏极的高性能亚微米mosfet的方法
公开(公告)号：US06168999A
公开(公告)日：2001-01-02
申请号：US09391301
申请日：1999-09-07
申请人： Qi Xiang , Wei Long
发明人： Qi Xiang , Wei Long
IPC分类号： H01L21336
CPC分类号： H01L29/66659 , H01L21/31155 , H01L29/665 , H01L29/66545 , H01L29/7835
摘要： The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, where the spacer facilitates formation of a lateral asymmetric channel; forming heavily doped extensions in the source side and the drain side, where the spacer prevents doping in the spacer area; removing the spacer; and forming a lightly doped extension in the drain side, where the heavily doped extensions and the lightly doped extension prevent hot carrier injection. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area. A lateral asymmetric channel is thus formed, and the speed of the submicron MOSFET is increased while simultaneously preventing hot carrier injection.
摘要翻译：本发明提供一种制造亚微米金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法包括在基板上设置栅极，该基板具有源极侧和漏极侧，漏极侧具有间隔区域; 在间隔区域形成间隔物; 在源极侧和漏极侧执行光晕注入，其中间隔物防止间隔区域中的注入，其中间隔物有助于形成横向不对称通道; 在源侧和漏极侧形成重掺杂的延伸，其中间隔物防止在间隔区中的掺杂; 去除间隔物; 并在漏极侧形成轻掺杂的延伸，其中重掺杂的延伸和轻掺杂的延伸部阻止热载流子注入。在优选实施例中，通过在栅极和衬底上沉积氧化物层，然后避免氧化物层在间隔区域中的氮注入，同时在氧化物层的其余部分中注入氮而形成间隔物。注入氮的氧化物和未注入氮的氧化物的蚀刻速率的差异允许选择性蚀刻氧化物层，导致间隔物在间隔区域中。因此形成横向非对称沟道，并且亚微米MOSFET的速度增加同时防止热载流子注入。

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