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1. 发明授权

US4754433A Dynamic ram having multiplexed twin I/O line pairs 失效
标题翻译：具有复用双I / O线对的动态RAM
公开(公告)号：US4754433A
公开(公告)日：1988-06-28
申请号：US908440
申请日：1986-09-16
申请人： Daeje Chin , Wei Hwang , Nicky C. Lu
发明人： Daeje Chin , Wei Hwang , Nicky C. Lu
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/1021 , G11C7/1033 , G11C7/1048
摘要： A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.
摘要翻译：动态随机存取存储器（DRAM）由第一和第二输入/输出（I / O）总线，第一和第二I / O读出放大器以及第一和第二I / O总线预充电电路组成。控制电路响应于模式控制信号的状态，以使得I / O总线和预充电电路的操作能够使得在一种操作模式下，DRAM以每个CAS循环页面模式以常规单位操作。在第二种操作模式下，实现了每个CAS循环页面模式的高速双位模式，其中I / O总线被交替使能，一个在CAS被断言时被使能，另一个在CAS被取消置位时使能。双位操作模式还用于对在其他总线使能的时段内未使能的I / O总线进行预充电。因此，在双位操作模式下，当CAS被断言并且当CAS被断言时，数据传送到DRAM或从DRAM发生的数据传输速率超过常规页面操作模式的数据传输速率。

2. 发明授权

US5021355A Method of fabricating cross-point lightly-doped drain-source trench transistor 失效
标题翻译：制造交叉点轻掺杂漏极 - 沟槽晶体管的方法
公开(公告)号：US5021355A
公开(公告)日：1991-06-04
申请号：US513711
申请日：1990-05-18
申请人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
发明人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
IPC分类号： H01L21/223 , H01L21/8242 , H01L27/108 , H01L27/112 , H01L29/78
CPC分类号： H01L27/10844 , H01L21/2236 , H01L27/10838 , H01L29/7827 , H01L29/7834 , H01L27/112
摘要： A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.
摘要翻译：用于自对准，轻掺杂漏极/源极n沟道场效应晶体管的结构和制造工艺，其中在衬底中的包括外延层的晶片的阱区中形成沟槽。在阱的表面上的沟槽周围形成第一重掺杂漏极区和位线元件，并且第二轻掺杂漏极区形成在靠近第一漏极区并且与沟槽侧壁自对准。源极区位于沟槽下面，其被多晶硅填充，其上方是栅极，并且另外的多晶硅形成传输字线。在沟槽侧壁处的阱区被掺杂以控制器件阈值电平，因此器件也位于字线/位线交叉点。

3. 发明授权

US4954731A Wordline voltage boosting circuits for complementary MOSFET dynamic memories 失效
标题翻译：用于互补MOSFET动态存储器的字线升压电路
公开(公告)号：US4954731A
公开(公告)日：1990-09-04
申请号：US344340
申请日：1989-04-26
申请人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
发明人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
IPC分类号： G11C11/407 , G11C11/408 , H03K5/02
CPC分类号： G11C11/4085 , H03K5/023
摘要： Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the first node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

4. 发明授权

US4833516A High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor 失效
标题翻译：具有与垂直沟槽电容器自对准的垂直沟槽晶体管的高密度存储单元结构及其制造方法
公开(公告)号：US4833516A
公开(公告)日：1989-05-23
申请号：US81270
申请日：1987-08-03
申请人： Wei Hwang , Nicky C. Lu
发明人： Wei Hwang , Nicky C. Lu
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10864 , H01L27/10841 , H01L29/7827 , H01L29/7834
摘要： A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

5. 发明授权

US4881105A Integrated trench-transistor structure and fabrication process 失效
标题翻译：集成沟槽晶体管结构和制造工艺
公开(公告)号：US4881105A
公开(公告)日：1989-11-14
申请号：US206148
申请日：1988-06-13
申请人： Bijan Davari , Wei Hwang , Nicky C. Lu
发明人： Bijan Davari , Wei Hwang , Nicky C. Lu
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/0925 , H01L29/66666 , H01L29/4236
摘要： An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

6. 发明授权

US4922128A Boost clock circuit for driving redundant wordlines and sample wordlines 失效
标题翻译：升压时钟电路，用于驱动冗余字线和样本字线
公开(公告)号：US4922128A
公开(公告)日：1990-05-01
申请号：US296995
申请日：1989-01-13
申请人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
发明人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
IPC分类号： G11C11/407 , G11C8/18 , G11C29/00
CPC分类号： G11C29/84 , G11C8/18
摘要： A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit are connected to the series pass FET transistors for enabling one or the other of the differnetially-connected FET transistors into conduction. The pair of capacitive coupling elements coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.

7. 发明授权

US4816884A High density vertical trench transistor and capacitor memory cell structure and fabrication method therefor 失效
标题翻译：高密度垂直沟槽晶体管和电容器存储单元的结构及其制造方法
公开(公告)号：US4816884A
公开(公告)日：1989-03-28
申请号：US75791
申请日：1987-07-20
申请人： Wei Hwang , Nicky C. Lu
发明人： Wei Hwang , Nicky C. Lu
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L29/78 , H01L27/02 , H01L29/06
CPC分类号： H01L27/10864 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate and an epitaxial layer disposed thereon. A relatively deep polysilicon filled trench is disposed in the epitaxial layer and substrate structure, the deep trench having a composite oxide/nitride insulation layer over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer over the deep trench region, the shallow trench having an oxide insulation layer on its vertical and horizontal surfaces thereof. A neck structure of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer on either side of the shallow trench to form semiconductor device drain junctions and polysilicon material is disposed in the shallow trench and over the epitaxial layer to form semiconductor device transfer gate and wordline regions respectively.

8. 发明授权

US08487684B2 Method for buffering clock skew by using a logical effort 有权
标题翻译：通过使用逻辑努力缓冲时钟偏移的方法
公开(公告)号：US08487684B2
公开(公告)日：2013-07-16
申请号：US13155523
申请日：2011-06-08
申请人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
发明人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.
摘要翻译：一种方法通过使用逻辑努力来缓冲时钟偏移，并且适用于停留在强反转区域，中等反转区域或弱反转区域中的时钟树。该方法包括在时钟树中建立温度传感器和可调宽度缓冲器，并且根据逻辑努力方程建立宽度和温度比较列表，对于可单独应用于强反转区域的可调宽度缓冲器，中等反演区域和弱反演区域; 从与时钟树停留的反转区域中的一个对应的宽度和温度比较列表中选择一个，使得温度传感器能够感测温度，并且在所选择的宽度和温度比较列表中搜索对应于温度的宽度由温度传感器感测; 并且使得可调宽度缓冲器能够根据所搜索的宽度执行宽度调制处理。

9. 发明授权

US08419274B2 Fully-on-chip temperature, process, and voltage sensor system 有权
标题翻译：全面的温度，过程和电压传感器系统
公开(公告)号：US08419274B2
公开(公告)日：2013-04-16
申请号：US12910199
申请日：2010-10-22
申请人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
发明人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , G01K2219/00
摘要： A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.
摘要翻译：完全片上的温度，过程和电压传感器包括电压传感器，过程传感器和温度传感器。温度传感器包括偏置电流发生器，环形振荡器，固定脉冲发生器，与门和第一计数器。偏置电流发生器根据芯片的工作电压产生与温度相关的输出电流。环形振荡器根据输出电流产生振荡信号。固定脉冲发生器产生固定的脉冲信号。与门连接到环形振荡器和固定脉冲发生器，用于对振荡信号和固定脉冲信号进行逻辑与运算，并产生温度传感器信号。

10. 发明授权

US08385149B2 Gate oxide breakdown-withstanding power switch structure 有权
标题翻译：栅极氧化物击穿电源开关结构
公开(公告)号：US08385149B2
公开(公告)日：2013-02-26
申请号：US13075682
申请日：2011-03-30
申请人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
发明人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.
摘要翻译：本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

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