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1. 发明申请

US20070281427A1 Bottom conductor for integrated MRAM 有权
标题翻译：集成MRAM的底部导体
公开(公告)号：US20070281427A1
公开(公告)日：2007-12-06
申请号：US11891923
申请日：2007-08-14
申请人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
发明人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
IPC分类号： H01L21/336
CPC分类号： H01L43/12 , H01L27/228
摘要： A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.
摘要翻译：描述了制造MTJ器件及其与CMOS集成电路的连接的方法。该设备由三层构建。底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。

2. 发明授权

US07265404B2 Bottom conductor for integrated MRAM 有权
标题翻译：集成MRAM的底部导体
公开(公告)号：US07265404B2
公开(公告)日：2007-09-04
申请号：US11215276
申请日：2005-08-30
申请人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
发明人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
IPC分类号： H01L29/76
CPC分类号： H01L43/12 , H01L27/228
摘要： A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.
摘要翻译：描述了非常适合于将MTJ设备连接到CMOS集成电路的结构。它由三层构建。底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。还描述了其形成方法。

3. 发明授权

US07358100B2 Bottom conductor for integrated MRAM 有权
标题翻译：集成MRAM的底部导体
公开(公告)号：US07358100B2
公开(公告)日：2008-04-15
申请号：US11891923
申请日：2007-08-14
申请人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
发明人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/228
摘要： A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.
摘要翻译：描述了一种制造MTJ器件及其与CMOS集成电路的连接的方法。该设备由三层构建。底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。

4. 发明申请

US20070045758A1 Bottom conductor for integrated MRAM 有权
公开(公告)号：US20070045758A1
公开(公告)日：2007-03-01
申请号：US11215276
申请日：2005-08-30
申请人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
发明人： Wei Cao , Chyu-Jiuh Torng , Cheng Horng , Ruying Tong , Chen-Jung Chien , Liubo Hong
IPC分类号： H01L43/00
CPC分类号： H01L43/12 , H01L27/228
摘要： A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

5. 发明申请

US20120085728A1 Novel process for MEMS scanning mirror with mass remove from mirror backside 有权
标题翻译： MEMS扫描镜的新工艺，从镜面背面去除质量
公开(公告)号：US20120085728A1
公开(公告)日：2012-04-12
申请号：US12924873
申请日：2010-10-07
申请人： Jun Chen , Guomin Mao , Tom Zhong , Wei Cao , Yee-Chung Fu , Chyu-Jiuh Torng
发明人： Jun Chen , Guomin Mao , Tom Zhong , Wei Cao , Yee-Chung Fu , Chyu-Jiuh Torng
IPC分类号： B81C1/00
CPC分类号： B81B3/0045 , B81B2201/042 , G02B26/0841
摘要： Two methods of fabricating a MEMS scanning mirror having a tunable resonance frequency are described. The resonance frequency of the mirror is set to a particular value by mass removal from the backside of the mirror during fabrication.
摘要翻译：描述制造具有可调共振频率的MEMS扫描反射镜的两种方法。反射镜的共振频率通过在制造期间从反射镜的背面质量去除而被设定为特定的值。

6. 发明授权

US08450119B2 Magnetic tunnel junction patterning using Ta/TaN as hard mask 有权
标题翻译：磁隧道结图案使用Ta / TaN作为硬掩模
公开(公告)号：US08450119B2
公开(公告)日：2013-05-28
申请号：US11378555
申请日：2006-03-17
申请人： Chyu-Jiuh Torng , Wei Cao , Terry Ko
发明人： Chyu-Jiuh Torng , Wei Cao , Terry Ko
IPC分类号： H01L29/82 , H01L21/00
CPC分类号： H01L43/12 , H01L43/08
摘要： An MTJ MRAM cell is formed by using a reactive ion etch (RIE) to pattern an MTJ stack on which there has been formed a bilayer Ta/TaN hard mask. The hard mask is formed by patterning a masking layer that has been formed by depositing a layer of TaN over a layer of Ta on the MTJ stack. After the stack is patterned, the TaN layer serves at least two advantageous purposes: 1) it protects the Ta layer from oxidation during the etching of the stack and 2) it serves as a surface having excellent adhesion properties for a subsequently deposited dielectric layer.
摘要翻译：通过使用反应离子蚀刻（RIE）来形成已经形成双层Ta / TaN硬掩模的MTJ叠层来形成MTJ MRAM电池。硬掩模通过图案化掩模层而形成，该掩模层通过在MTJ堆叠上的Ta层上沉积TaN层而形成。在堆叠被图案化之后，TaN层起至少两个有利的作用：1）它在保护叠层的过程中保护Ta层免受氧化，2）它用作随后沉积的介电层具有优异粘合性能的表面。

7. 发明申请

US20130043471A1 Magnetic tunnel junction for MRAM applications 有权
公开(公告)号：US20130043471A1
公开(公告)日：2013-02-21
申请号：US13136929
申请日：2011-08-15
申请人： Wei Cao , Witold Kula , Chyu-Jiuh Torng
发明人： Wei Cao , Witold Kula , Chyu-Jiuh Torng
IPC分类号： H01L29/04 , H01L21/36
CPC分类号： H01L43/10 , B82Y40/00 , H01F10/3272 , H01F10/3295 , H01F41/307 , H01L43/12
摘要： Reading margin is improved in a MTJ designed for MRAM applications by employing a pinned layer with an AP2/Ru/AP1 configuration wherein the AP1 layer is a CoFeB/CoFe composite and by forming a MgO tunnel barrier adjacent to the CoFe AP1 layer by a sequence that involves depositing and oxidizing a first Mg layer with a radical oxidation (ROX) process, depositing and oxidizing a second Mg layer with a ROX method, and depositing a third Mg layer on the oxidized second Mg layer. The third Mg layer becomes oxidized during a subsequent anneal. MTJ performance may be further improved by selecting a composite free layer having a Fe/NiFeHf or CoFe/Fe/NiFeHf configuration where the NiFeHf layer adjoins a capping layer in a bottom spin valve configuration. As a result, read margin is optimized simultaneously with improved MR ratio, a reduction in bit line switching current, and a lower number of shorted bits.

8. 发明申请

US20120181537A1 Magnetic Tunnel Junction for MRAM applications 有权
标题翻译： MRAM应用的磁隧道结
公开(公告)号：US20120181537A1
公开(公告)日：2012-07-19
申请号：US12930877
申请日：2011-01-19
申请人： Wei Cao , Cheng T. Horng , Witold Kula , Chyu Jiuh Torng
发明人： Wei Cao , Cheng T. Horng , Witold Kula , Chyu Jiuh Torng
IPC分类号： H01L29/82 , H01L21/36 , H01L29/04
CPC分类号： H01L43/10 , G11C11/161 , H01L27/222 , H01L43/00 , H01L43/02 , H01L43/08
摘要： A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous NiFeX layer for improved bit switching performance. The crystalline layer is Fe, Ni, or FeB with a thickness of at least 6 Angstroms which affords a high magnetoresistive ratio. The X element in the NiFeX layer is Mg, Hf, Zr, Nb, or Ta with a content of 5 to 30 atomic %. NiFeX thickness is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. In an alternative embodiment, the crystalline layer may be a Fe/NiFe bilayer. Optionally, the amorphous layer may have a NiFeM1/NiFeM2 configuration where M1 and M2 are Mg, Hf, Zr, Nb, or Ta, and M1 is unequal to M2. Annealing at 300° C. to 360° C. provides a high magnetoresistive ratio of about 150%.
摘要翻译：公开了具有接触隧道势垒的较低结晶层和上部非晶NiFeX层的复合自由层的MRAM阵列中的MTJ，用于改善位切换性能。结晶层是厚度至少为6埃的Fe，Ni或FeB，其具有高的磁阻比。 NiFeX层中的X元素为含有5〜30原子％的Mg，Hf，Zr，Nb或Ta。 NiFeX厚度优选在20至40埃之间，以显着减少位线切换电流和短路位数。在替代实施例中，结晶层可以是Fe / NiFe双层。可选地，非晶层可以具有其中M1和M2是Mg，Hf，Zr，Nb或Ta的NiFeM1 / NiFeM2构型，M1不等于M2。在300℃至360℃退火，提供约150％的高磁阻比。

9. 发明授权

US08492169B2 Magnetic tunnel junction for MRAM applications 有权
标题翻译：用于MRAM应用的磁隧道结
公开(公告)号：US08492169B2
公开(公告)日：2013-07-23
申请号：US13136929
申请日：2011-08-15
申请人： Wei Cao , Witold Kula , Chyu-Jiuh Torng
发明人： Wei Cao , Witold Kula , Chyu-Jiuh Torng
IPC分类号： H01L29/82 , H01L29/88 , G11C11/02
CPC分类号： H01L43/10 , B82Y40/00 , H01F10/3272 , H01F10/3295 , H01F41/307 , H01L43/12
摘要： Reading margin is improved in a MTJ designed for MRAM applications by employing a pinned layer with an AP2/Ru/AP1 configuration wherein the AP1 layer is a CoFeB/CoFe composite and by forming a MgO tunnel barrier adjacent to the CoFe AP1 layer by a sequence that involves depositing and oxidizing a first Mg layer with a radical oxidation (ROX) process, depositing and oxidizing a second Mg layer with a ROX method, and depositing a third Mg layer on the oxidized second Mg layer. The third Mg layer becomes oxidized during a subsequent anneal. MTJ performance may be further improved by selecting a composite free layer having a Fe/NiFeHf or CoFe/Fe/NiFeHf configuration where the NiFeHf layer adjoins a capping layer in a bottom spin valve configuration. As a result, read margin is optimized simultaneously with improved MR ratio, a reduction in bit line switching current, and a lower number of shorted bits.
摘要翻译：通过采用具有AP2 / Ru / AP1配置的钉扎层，其中AP1层是CoFeB / CoFe复合材料并且通过顺序形成与CoFe AP1层相邻的MgO隧道势垒，为MRAM应用设计的MTJ中的读取余量得到改善其包括用自由基氧化（ROX）工艺沉积和氧化第一Mg层，用ROX法沉积和氧化第二Mg层，以及在氧化的第二Mg层上沉积第三Mg层。在随后的退火中，第三Mg层变成氧化的。通过选择具有Fe / NiFeHf或CoFe / Fe / NiFeHf构型的复合自由层，其中NiFeHf层与底部自旋阀结构中的覆盖层邻接，可以进一步改善MTJ性能。结果，读取余量同时优化了MR比，降低了位线切换电流，并且更少的短路位数。

10. 发明授权

US07122386B1 Method of fabricating contact pad for magnetic random access memory 有权
标题翻译：制造磁性随机存取存储器接触焊盘的方法
公开(公告)号：US07122386B1
公开(公告)日：2006-10-17
申请号：US11231674
申请日：2005-09-21
申请人： Chyu-Jiuh Torng , Tom Zhong , Wei Cao , Po-Kang Wang
发明人： Chyu-Jiuh Torng , Tom Zhong , Wei Cao , Po-Kang Wang
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.
摘要翻译：描述了在字线焊盘（WLP）和位线（BL）触点之间形成Cu-Cu结的方法。在包括WLP和字线的衬底上的第一SiN x层中形成WL触点上方的开口。在底电极（BE）层，MTJ叠层和硬掩模之后，顺序沉积，蚀刻在字线之上形成MTJ元件。另一蚀刻形成BE，并使WLP和接合焊盘（BP）上方的第一SiN x层暴露。沉积MTJ ILD层并平坦化，随后沉积第二SiN x层和BL ILD层。沟槽形成在WLP，硬掩模和BP之上的BL ILD层和第二SiN x x层中。在WLP和BP上方的MTJ ILD和第一SiN x x层中形成通孔之后，随后进行Cu沉积以形成双镶嵌BL触点。

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