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    • 6. 发明授权
    • Stacked silicon-controlled rectifier having a low voltage trigger and
adjustable holding voltage for ESD protection
    • 堆叠的可控硅整流器具有低电压触发和可调保持电压用于ESD保护
    • US6016002A
    • 2000-01-18
    • US993820
    • 1997-12-18
    • Julian Zhiliang ChenThomas A. VrotsosWayne T. Chen
    • Julian Zhiliang ChenThomas A. VrotsosWayne T. Chen
    • H01L29/74H01L23/60H01L27/02H02H7/20H02H9/04H05F3/02H01L23/62H01L29/00H01L31/111
    • H01L27/0262H01L27/0266H01L2924/0002
    • An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128) is approximately equal to the sum of the individual holding voltages for the SCRs (126, 128), which overall holding voltage is greater than the trigger voltage. Preferably, the SCR (68) is isolated from the P substrate (92) by a P-N junction which is provided by disposing the SCR (68) within an N-tank (98).
    • 提供了用于保护集成电路(62)抵抗ESD事件的SCR(68),其具有响应于施加到集成电路(62)的功率而被自动调整到不同触发电压电平的触发电压。 提供增强型P沟道晶体管(78)用于确定触发电压。 当工作电源未被施加到集成电路(62)时,P沟道晶体管(78)阈值电压确定触发SCR(68)的电压。 当工作电源施加到集成电路(62)时,工作电压被施加到P沟道晶体管(78)的栅极,然后P沟道晶体管(78)的工作电压和阈值电压 确定SCR(68)的触发电压。 然后,形成SCR(68)的PNP和NPN晶体管对(76,80)被锁存以将受保护的信号路径(69)分流到地。 SCR(68)保持锁存,直到施加到信号路径(69)的电压落在SCR(68)的保持电压以下。 多个SCR(126,128)可以串联连接,使得SCR系列(126,128)的整体保持电压近似等于SCR的各个保持电压之和(126,128 ),其总保持电压大于触发电压。 优选地,SCR(68)通过将SCR(68)设置在N-罐(98)内而提供的P-N结与P基板(92)隔离。
    • 7. 发明授权
    • Zener diode structure with high reverse breakdown voltage
    • 具有高反向击穿电压的齐纳二极管结构
    • US5869882A
    • 1999-02-09
    • US724575
    • 1996-09-30
    • Wayne T. ChenRoss E. TeggatzTaylor R. Efland
    • Wayne T. ChenRoss E. TeggatzTaylor R. Efland
    • H01L29/866H01L29/861H01L31/107
    • H01L29/866H01L29/0692H01L29/402H01L29/66106
    • A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region. Structure is provided between the first and second regions for repelling majority charge carriers associated with the opposite conductivity type which can be a field plate spaced from the first tank; a portion at the surface of the first tank having the first conductivity type; or a tank, of first conductivity type disposed in the first tank, abutting the first region, extending more deeply into the first tank than does the first region and more lightly doped than the first region. In accordance with a further embodiment, the diode includes a semiconductor substrate, a first tank portion disposed in the substrate and a second tank portion disposed in the first tank portion as in the prior embodiments. A first region of first conductivity type is disposed in the second tank portion and extends into the first tank portion. A second region of opposite conductivity type more highly doped than the first tank portion is disposed in the first tank portion and spaced from the first region.
    • 能够以比现有技术高得多的电压击穿的齐纳二极管通过提供具有设置在其中的具有相反导电类型的第一容器的第一导电类型的半导体衬底来制造。 第一罐包括相对较低和相对较高的电阻率部分,相对较低的掺杂部分将相对较高的掺杂部分与衬底隔离。 第一导电类型的第一区域设置在较高掺杂部分中,并且具有相反导电类型的第二区域和比第一容器更高掺杂的第二区域与第一区域间隔开。 在第一和第二区域之间提供结构,用于排斥与相反导电类型相关联的多数电荷载体,其可以是与第一罐间隔开的场板; 第一罐的表面上具有第一导电类型的部分; 或第一导电类型的罐,邻接第一区域,比第一区域更深地延伸到第一槽中,并且比第一区域更轻地掺杂。 根据另一实施例,二极管包括半导体衬底,设置在衬底中的第一容器部分和如先前实施例中那样设置在第一容器部分中的第二容器部分。 第一导电类型的第一区域设置在第二罐部分中并延伸到第一罐部分中。 与第一容器部分相比更高掺杂的相反导电类型的第二区域设置在第一罐部分中并与第一区域间隔开。
    • 8. 发明授权
    • Method and apparatus for high voltage level shifting
    • 高压电平转换的方法和装置
    • US5539334A
    • 1996-07-23
    • US991622
    • 1992-12-16
    • John S. Clapp, IIIWayne T. Chen
    • John S. Clapp, IIIWayne T. Chen
    • H03K3/356H03K17/10H03K19/0185H03K19/003
    • H03K17/102H03K3/356017H03K3/356113
    • A voltage level shifter circuit (10) for outputting an output high (18) and output low (18) signal is provided which accommodates multiple power supplies (12 and 22) at different relative voltage to each other. The voltage level shifter (10) includes an input stage (24) which is characterized by voltage ranges applicable to the process used to make the circuit. The voltage level shifter circuit includes an output stage (18) which is also characterized by the same voltage ranges which cannot be exceeded. The output stage outputs the translated output high (16) and output low (18) voltage signals. A clamping network (20) is employed to ensure that the output stage voltage ranges are not exceeded. The present invention implements a high voltage level shifter (10) using low voltage components by extending the breakdown capability of the voltage level shifter circuit (10) past the breakdown voltage of any single component in the circuit.
    • 提供了用于输出高输出(18)和输出低(18)信号的电压电平移位器电路(10),其以彼此不同的相对电压容纳多个电源(12和22)。 电压电平转换器(10)包括输入级(24),其特征在于适用于用于制造电路的工艺的电压范围。 电压电平移位电路包括输出级(18),其特征还在于不能超过相同的电压范围。 输出级输出转换输出高电平(16)和输出低电平(18)电压信号。 采用夹紧网络(20)来确保不超过输出级电压范围。 本发明通过将电压电平移位器电路(10)的击穿能力延伸超过电路中任何单个部件的击穿电压来实现使用低电压分量的高电压电平转换器(10)。