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1. 发明授权

US4626825A Logarithmic conversion apparatus 失效
标题翻译：对数转换装置
公开(公告)号：US4626825A
公开(公告)日：1986-12-02
申请号：US751305
申请日：1985-07-02
申请人： Wayne P. Burleson , Lawrence F. Wagner , Korbin S. Van Dyke
发明人： Wayne P. Burleson , Lawrence F. Wagner , Korbin S. Van Dyke
IPC分类号： G06F1/03 , H03M7/24 , H03M7/50
CPC分类号： H03M7/24 , G06F1/0307 , G06F7/4833
摘要： A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number. A decoder receives the exponential component of the logarithmic representation and a Point Set Output value, a scale value for said integer, and supplies a shifted signal. The shifted signal is supplied to a shifter along with the first number and the shifter shifts the first number by the shift signal to produce the integer.
摘要翻译：公开了一种用于将数字二进制整数转换成对数表示并将对数表示转换成数字二进制整数的对数转换装置。该装置确定整数的前导非零位的位位置，使整数移位，使得前导非零位是最左位。查找表接收移位的整数，并提供代表移位数的对数的尾数部分的数字。编码器接收点集输入值，所述整数的比例值，并且二进制位置的数量被移位，并且生成整数的对数的指数部分。为了将数字的对数表示转换为整数表示，装置具有接收对数表示的尾数分量并且提供第一数字的查找表。解码器接收对数表示的指数分量和点集输出值，所述整数的比例值，并提供移位信号。移位信号与第一个数字一起提供给移位器，移位器将第一个数字移位移位信号以产生整数。

2. 发明授权

US4862346A Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses 失效
标题翻译：使用同时接收的当前，更改，测试和重新加载地址更新地址的寄存器文件的索引
公开(公告)号：US4862346A
公开(公告)日：1989-08-29
申请号：US751304
申请日：1985-07-02
申请人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
发明人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
IPC分类号： G06F1/03
CPC分类号： G06F1/0307
摘要： A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register. The logarithmic calculator receives the logarithmic data from the data register, operates it thereon, and supplies the resultant logarithmic calculation to the data register for storage. The data converter also communicates with the data register, receives the logarithmic data therefrom and reconverts it back into integer data to be ultimately supplied to the data register. The controller controls the operation of the data converter, data register, and the logarithmic calculator through the internal program instructions supplied on the internal bus.
摘要翻译：数字处理器具有四个部件：控制器，数据转换器，数据寄存器和对数计算器。处理器具有地址总线和与其通信的数据总线。地址总线连接到控制器。数据总线连接到控制器和数据寄存器。来自数据总线的程序指令被提供给控制器，数据总线上的数据被提供给数据寄存器。提供给控制器的程序指令被解码，内部程序指令由控制器产生。控制器通过内部总线通过内部程序指令与数据转换器，数据寄存器和对数计算器进行通信。来自数据总线的整数数据存储在数据寄存器中。数据转换器接收整数数据，将其转换为对数数据，并将其存储在数据寄存器中。对数计算器从数据寄存器接收对数数据，对其进行运算，并将所得到的对数运算提供给数据寄存器进行存储。数据转换器还与数据寄存器进行通信，从其接收对数数据，并将其重新转换为最终提供给数据寄存器的整数数据。控制器通过内部总线上提供的内部程序指令控制数据转换器，数据寄存器和对数计算器的操作。

3. 发明授权

US5109524A Digital processor with a four part data register for storing data before and after data conversion and data calculations 失效
标题翻译：数字处理器具有四部分数据寄存器，用于在数据转换和数据计算之前和之后存储数据
公开(公告)号：US5109524A
公开(公告)日：1992-04-28
申请号：US263905
申请日：1988-10-28
申请人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
发明人： Lawrence F. Wagner , Korbin S. Van Dyke , Wayne P. Burleson , Robert D. Hemming , John P. Guadagna
IPC分类号： G06F1/03
CPC分类号： G06F1/0307
摘要： A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register. The logarithmic calculator receives the logarithmic data from the data register, operates it thereon, and supplies the resultant logarithmic calculation to the data register for storage. The data converter also communicates with the data register, receives the logarithmic data therefrom and reconverts it back into integer data to be ultimately supplied to the data register. The controller controls the operation of the data converter, data register, and the logarithmic calculator through the internal program instructions supplied on the internal bus.
摘要翻译：数字处理器具有控制器，数据转换器，数据寄存器和对数计算器。处理器具有地址总线和与其通信的数据总线。地址总线连接到控制器。数据总线连接到控制器和数据寄存器。来自数据总线的程序指令被提供给控制器，数据总线上的数据被提供给数据寄存器。提供给控制器的程序指令被解码，内部程序指令由控制器产生。控制器通过内部总线通过内部程序指令与数据转换器，数据寄存器和对数计算器进行通信。来自数据总线的整数数据存储在数据寄存器中。数据转换器接收整数数据，将其转换为对数数据，并将其存储在数据寄存器中。对数计算器从数据寄存器接收对数数据，对其进行运算，并将所得到的对数运算提供给数据寄存器进行存储。数据转换器还与数据寄存器进行通信，从其接收对数数据，并将其重新转换为最终提供给数据寄存器的整数数据。控制器通过内部总线上提供的内部程序指令控制数据转换器，数据寄存器和对数计算器的操作。

4. 发明授权

US4852038A Logarithmic calculating apparatus 失效
标题翻译：对数计算装置
公开(公告)号：US4852038A
公开(公告)日：1989-07-25
申请号：US751302
申请日：1985-07-02
申请人： Lawrence F. Wagner , Wayne P. Burleson , Korbin S. Van Dyke
发明人： Lawrence F. Wagner , Wayne P. Burleson , Korbin S. Van Dyke
IPC分类号： G06F1/03
CPC分类号： G06F1/0307
摘要： A calculating apparatus receives four operands ("a, b, c and d") simultaneously. A first multiplier/divider performs the calculation of a*b or a.div.b and provides an output u. A second multiplier/divider performs the calculation of c*d or c.div.d and provides an output v. An adder/subtractor receives u and v and performed the calculation of u+v and u-v. A controller controls the operation of the first and second multiplier/divider to select the operation of multiplication or division.
摘要翻译：计算装置同时接收四个操作数（“a，b，c和d”）。第一乘法器/除法器执行a * b或DIVIDED b的计算，并提供输出u。第二乘法器/分频器执行c * d或c DIVIDED d的计算，并提供输出v。加法器/减法器接收u和v并执行u + v和u-v的计算。控制器控制第一和第二乘法器/除法器的操作以选择乘法或除法的操作。

5. 发明授权

US08788792B2 Apparatus for executing programs for a first computer architecture on a computer of a second architecture 有权
标题翻译：一种用于在第二架构的计算机上执行用于第一计算机体系结构的程序的装置
公开(公告)号：US08788792B2
公开(公告)日：2014-07-22
申请号：US13371766
申请日：2012-02-13
申请人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , Matthew F. Storch , Sandeep Nijhawan , Dale R. Jurich , Korbin S. Van Dyke
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/45554 , G06F9/30174 , G06F9/30189 , G06F9/3861
摘要： A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
摘要翻译：多指令集架构（ISA）计算机系统包括计算机程序，第一处理器，第二处理器，轮廓仪和翻译器。计算机程序包括第一ISA的指令，第一ISA具有第一复杂度。第一处理器被配置为执行第一ISA的指令。第二处理器被配置为执行第二ISA的指令，第二ISA不同于第一ISA并且具有第二复杂度，其中第二复杂度小于第一复杂度。分析器被配置为选择用于转换为第二ISA的指令的计算机程序的块，其中该块包括第一ISA的一个或多个指令。翻译器被配置为将第一ISA的块转换为第二ISA的指令以供第二处理器执行。

6. 发明申请

US20090300323A1 Vector Processor System 有权
标题翻译：矢量处理器系统
公开(公告)号：US20090300323A1
公开(公告)日：2009-12-03
申请号：US12475393
申请日：2009-05-29
申请人： Richard Hessel , Chetana N. Keltcher , Nathan Daniel Tuck , Korbin S. Van Dyke
发明人： Richard Hessel , Chetana N. Keltcher , Nathan Daniel Tuck , Korbin S. Van Dyke
IPC分类号： G06F15/76 , G06F9/02 , G06F12/02
CPC分类号： G11C7/1072 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F15/8061
摘要： A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.
摘要翻译：矢量处理系统使用片上系统（SOC）实现技术提供高性能矢量处理。一个或多个标量处理器（或核）与矢量处理器一起操作，并且处理器共同共享对耦合到动态随机存取读/写存储器（DRAM）的多个存储器接口的访问。在典型实施例中，向量处理器作为标量处理器的从属单元操作，响应于从标量处理器接收的命令执行计算密集型单指令多数据（SIMD）代码。向量处理器实现包括机器状态，指令集，异常模型和存储器模型的向量处理指令集体系结构（ISA）。

7. 发明授权

US06954923B1 Recording classification of instructions executed by a computer 有权
标题翻译：记录计算机执行指令的分类
公开(公告)号：US06954923B1
公开(公告)日：2005-10-11
申请号：US09348317
申请日：1999-07-07
申请人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
发明人： John S. Yates, Jr. , David L. Reese , Korbin S. Van Dyke
IPC分类号： G06F9/318 , G06F9/38 , G06F9/42 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/30174 , G06F9/30189 , G06F9/3802 , G06F9/3861 , G06F9/4486
摘要： An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.
摘要翻译：一个执行两个指令集的指令处理器。指令存储在单个地址空间的不同虚拟存储器页面中，并且被编码用于两个不同指令集的计算机，并且使用两种不同的调用约定。指令处理器根据存储在对应于指令的存储器页的表条目中的第一标志的指示，来解释第一或第二指令集下的指令。处理器识别何时使用第二数据存储约定将使用第一数据存储约定的指令页面的程序执行转移到指令页，如由表条目中存储的第二标志所指示的，然后调整数据存储内容的计算机从第一存储惯例到第二数据存储惯例。历史记录提供了最近执行的指令的分类记录。

8. 发明授权

US5881265A Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts 失效
公开(公告)号：US5881265A
公开(公告)日：1999-03-09
申请号：US463459
申请日：1995-06-05
申请人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
发明人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John Gregory Favor , Dale R. Greenley , Robert A. Cargnoni
IPC分类号： G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/38 , G06F11/36 , G06F15/78
CPC分类号： G06F11/3648 , G06F15/8053 , G06F9/30003 , G06F9/30018 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30189 , G06F9/34 , G06F9/3555 , G06F9/38 , G06F9/3804 , G06F9/3812 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F9/3885
摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

9. 发明授权

US5590351A Superscalar execution unit for sequential instruction pointer updates and segment limit checks 失效
标题翻译：超标量执行单元，用于顺序指令指针更新和段限制检查
公开(公告)号：US5590351A
公开(公告)日：1996-12-31
申请号：US185488
申请日：1994-01-21
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/32 , G06F9/321 , G06F9/3863
摘要： An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.
摘要翻译：执行单元在一个周期内执行多个顺序指令指针更新和段限制检查。更新和检查在推测性地执行可变长度指令的高性能流水线处理器中进行。执行单元的公开的实施例包括下一个EIP（扩展指令指针）选择逻辑，当前EIP选择逻辑，EIP历史RAM，双EIP加法器，CS限制检验加法器，极限检查组合逻辑和限制故障历史RAM 。

10. 发明授权

US5327547A Two-level branch prediction cache 失效
标题翻译：两级分支预测缓存
公开(公告)号：US5327547A
公开(公告)日：1994-07-05
申请号：US954441
申请日：1992-09-30
申请人： David R. Stiles , John G. Favor , Korbin S. Van Dyke
发明人： David R. Stiles , John G. Favor , Korbin S. Van Dyke
IPC分类号： G06F9/38 , G06F12/08 , G06F13/00
CPC分类号： G06F9/3806 , G06F9/3804 , G06F9/3848
摘要： An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
摘要翻译：利用混合缓存结构的改进的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。

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