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1. 发明授权

US5590351A Superscalar execution unit for sequential instruction pointer updates and segment limit checks 失效
标题翻译：超标量执行单元，用于顺序指令指针更新和段限制检查
公开(公告)号：US5590351A
公开(公告)日：1996-12-31
申请号：US185488
申请日：1994-01-21
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/32 , G06F9/321 , G06F9/3863
摘要： An execution unit performs multiple sequential instruction pointer updates and segment limit checks within a cycle. The updates and checks are carried out in a high-performance pipelined processor that speculatively executes variable length instructions. A disclosed embodiment of the execution unit includes Next EIP (Extended Instruction Pointer) selection logic, Current EIP selection logic, an EIP History RAM, a Dual EIP Adder, a CS Limit check adder, limit checking combinational logic, and a limit fault History RAM.
摘要翻译：执行单元在一个周期内执行多个顺序指令指针更新和段限制检查。更新和检查在推测性地执行可变长度指令的高性能流水线处理器中进行。执行单元的公开的实施例包括下一个EIP（扩展指令指针）选择逻辑，当前EIP选择逻辑，EIP历史RAM，双EIP加法器，CS限制检验加法器，极限检查组合逻辑和限制故障历史RAM 。

2. 发明授权

US5675758A Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations 失效
标题翻译：具有主要整数执行单元的处理器和用于执行无序添加和移动操作的补充整数执行单元
公开(公告)号：US5675758A
公开(公告)日：1997-10-07
申请号：US340183
申请日：1994-11-15
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： G06F9/315 , G06F9/32 , G06F9/34 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/34 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3893
摘要： The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.
摘要翻译：通过添加称为添加/移动单元（AMU）的补充整数执行单元来增加高性能处理器的现有执行单元，该单元执行选择添加并且相对于其他执行单位。以较小的增量成本，AMU可以更好地利用现有的地址准备单元（AP）的昂贵的有限资源，处理线性和物理地址生成用于存储器操作数引用，控制传输和页面交叉。 AMU删除数据依赖关系，从而增加可用的指令级并行性。处理器执行无序和推测执行的能力易于利用增加的指令级并行性，结果提高了性能。

3. 发明授权

US06195745B1 Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit 失效
标题翻译：通过并行无序执行添加和移动的补充整数执行单元中的管道吞吐量
公开(公告)号：US06195745B1
公开(公告)日：2001-02-27
申请号：US09080492
申请日：1998-05-18
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： C06F930
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/34 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3863 , G06F9/3893
摘要： The existing execution units of a high-performance processor are augmented by tile addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.
摘要翻译：高性能处理器的现有执行单元通过添加称为添加/移动单元（AMU）的补充整数执行单元来增加，其执行选择添加并且相对于其他执行单位。以较小的增量成本，AMU可以更好地利用现有的地址准备单元（AP）的昂贵的有限资源，处理线性和物理地址生成用于存储器操作数引用，控制传输和页面交叉。 AMU删除数据依赖关系，从而增加可用的指令级并行性。处理器执行无序和推测执行的能力易于利用增加的指令级并行性，结果提高了性能。

4. 发明授权

US5802339A Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit 失效
标题翻译：通过并行无序执行添加和移动的补充整数执行单元中的管道吞吐量
公开(公告)号：US5802339A
公开(公告)日：1998-09-01
申请号：US801709
申请日：1997-02-14
申请人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
发明人： Elliot A. Sowadsky , Larry Widigen , David L. Puziol , Korbin S. Van Dyke
IPC分类号： G06F9/315 , G06F9/32 , G06F9/34 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/30032 , G06F9/30094 , G06F9/30167 , G06F9/34 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3893
摘要： The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.
摘要翻译：通过添加称为添加/移动单元（AMU）的补充整数执行单元来增加高性能处理器的现有执行单元，该单元执行选择添加并且相对于其他执行单位。以较小的增量成本，AMU可以更好地利用现有的地址准备单元（AP）的昂贵的有限资源，处理线性和物理地址生成用于存储器操作数引用，控制传输和页面交叉。 AMU删除数据依赖关系，从而增加可用的指令级并行性。处理器执行无序和推测执行的能力易于利用增加的指令级并行性，结果提高了性能。

5. 发明授权

US5623614A Branch prediction cache with multiple entries for returns having multiple callers 失效
标题翻译：具有多个条目的分支预测缓存，具有多个呼叫者
公开(公告)号：US5623614A
公开(公告)日：1997-04-22
申请号：US122922
申请日：1993-09-17
申请人： Korbin S. Van Dyke , Larry Widigen , David L. Puziol
发明人： Korbin S. Van Dyke , Larry Widigen , David L. Puziol
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3808
摘要： A Branch Prediction Cache (BPC) selects from among multiple branch address entries for a single return-type instruction that returns to multiple callers. The BPC has a branch address associative memory, a return address associative memory, and word line logic used to validate and qualify entries. The branch address associative memory monitors program addresses for previously stored branch addresses. The return address stack (RtnStack) stores the return addresses for the most recent call-type instructions. The top of the stack is input to the return address associative memory. When a program address has multiple matches in the branch address associative memory, the return address associative memory enables only the entry that has an associated return address matching the top of the RtnStack. In an alternate embodiment, the return address associative memory is combined with a branch address cache and target address associative memory.
摘要翻译：分支预测缓存（BPC）从多个分支地址条目中选择返回多个呼叫者的单个返回类型指令。 BPC具有分支地址关联存储器，返回地址关联存储器和用于验证和限定条目的字线逻辑。分支地址关联存储器监视先前存储的分支地址的程序地址。返回地址堆栈（RtnStack）存储最近的呼叫类型指令的返回地址。堆栈的顶部输入到返回地址关联存储器。当程序地址在分支地址关联存储器中具有多个匹配时，返回地址关联存储器仅使具有与RtnStack顶部匹配的关联返回地址的条目。在替代实施例中，返回地址关联存储器与分支地址高速缓存和目标地址关联存储器组合。

6. 发明授权

US5815699A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US5815699A
公开(公告)日：1998-09-29
申请号：US472698
申请日：1995-06-06
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

7. 发明授权

US5454117A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US5454117A
公开(公告)日：1995-09-26
申请号：US112572
申请日：1993-08-25
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein B. Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein B. Smith, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

8. 发明授权

US06671798B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06671798B1
公开(公告)日：2003-12-30
申请号：US09992822
申请日：2001-11-16
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

9. 发明授权

US06360318B1 Configurable branch prediction for a processor performing speculative execution 失效
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06360318B1
公开(公告)日：2002-03-19
申请号：US09608451
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。可以通过编程方式在软件中完成配置。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一个状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

10. 发明授权

US06282639B1 Configurable branch prediction for a processor performing speculative execution 有权
标题翻译：执行推测执行的处理器的可配置分支预测
公开(公告)号：US06282639B1
公开(公告)日：2001-08-28
申请号：US09608448
申请日：2000-06-29
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein Bennett Smith, III
IPC分类号： G06F900
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss Information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.
摘要翻译：在本发明的第一方面中，包括逻辑和互连的分支预测硬件可经由控制线进行配置，以改变生成分支预测的方式。该配置可以通过软件进行编程。或者，可以通过硬件来响应处理器事件来进行配置。这样的处理器事件包括CS寄存器的加载和指令工作量的变化。在本发明的第二方面中，与推测执行相关，部分地基于解决的分支历史信息来预测多个分支的方向。然后针对每个预测分支存储暂定分支历史信息。当解决预测分支时，根据所存储的用于最近解决的分支的临时分支历史信息来更新所解析的分支历史信息。此外，预测可能部分基于前述未解决的分支预测（如果有）是未完成的。在本发明的第三方面中，来自分支预测高速缓存（BPC）的命中/错误信息可以可选地用于制定存储在基于相关的分支历史表中的寻址的两位计数器的下一状态值。由于BPC中的小姐可能会指出最近没有遇到这个分支，所以无论目前存在什么状态，都可以强制执行到仅基于分支是否被解决的状态。可以在软件控制下启用和禁用此功能。在本发明的第四方面中，可选地使用来自指令解码器的信息来覆盖用于选择分支指令的基于相关性的基于分支历史表的预测。可以在软件或硬件控制下启用和禁用此功能。

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