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1. 发明授权

US08173508B2 Semiconductor device having vertical type MOSFET and manufacturing method thereof 失效
标题翻译：具有垂直型MOSFET的半导体器件及其制造方法
公开(公告)号：US08173508B2
公开(公告)日：2012-05-08
申请号：US12591883
申请日：2009-12-03
申请人： Wataru Sumida , Kenya Kobayashi
发明人： Wataru Sumida , Kenya Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/26586 , H01L29/0619 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.
摘要翻译：一种方法（和结果）包括形成具有多个条状沟槽的半导体层，形成部分地埋设在多个沟槽中的每一个中的栅电极，并且在形成栅电极之后通过离子注入将杂质引入半导体层。栅电极具有形成在每个沟槽中的掩埋部分和位于掩埋部分上方并且具有大于掩埋部分的宽度的突出部分。引入杂质包括通过倾斜离子注入将杂质引入到突出部分下方的半导体层中。

2. 发明授权

US07807531B2 Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps 失效
标题翻译：具有沟槽式栅极的半导体器件及其制造方法能够简化制造步骤
公开(公告)号：US07807531B2
公开(公告)日：2010-10-05
申请号：US12453551
申请日：2009-05-14
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4925 , H01L29/511 , H01L29/518 , H01L29/66734
摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.
摘要翻译：在半导体器件中，在半导体晶片的沟槽内形成栅极二氧化硅层。第一栅电极经由栅极二氧化硅层形成在半导体晶片的沟槽的侧壁上。绝缘层经由栅极二氧化硅层形成在半导体晶片的沟槽的底部上并被第一栅电极包围。绝缘层不包括二氧化硅，并且具有与二氧化硅不同的蚀刻特性。第二栅电极被埋在半导体晶片的沟槽中，并与第一栅电极和绝缘层接触。

3. 发明申请

US20100155833A1 Semiconductor device having vertical type MOSFET and manufacturing method thereof 失效
标题翻译：具有垂直型MOSFET的半导体器件及其制造方法
公开(公告)号：US20100155833A1
公开(公告)日：2010-06-24
申请号：US12591883
申请日：2009-12-03
申请人： Wataru Sumida , Kenya Kobayashi
发明人： Wataru Sumida , Kenya Kobayashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2253 , H01L21/26586 , H01L29/0619 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation.
摘要翻译：一种方法（和结果）包括形成具有多个条状沟槽的半导体层，形成部分地埋设在多个沟槽中的每一个中的栅电极，并且在形成栅电极之后通过离子注入将杂质引入半导体层。栅电极具有形成在每个沟槽中的掩埋部分和位于掩埋部分上方并且具有大于掩埋部分的宽度的突出部分。引入杂质包括通过倾斜离子注入将杂质引入到突出部分下方的半导体层中。

4. 发明授权

US06770539B2 Vertical type MOSFET and manufacturing method thereof 失效
标题翻译：垂直型MOSFET及其制造方法
公开(公告)号：US06770539B2
公开(公告)日：2004-08-03
申请号：US10421829
申请日：2003-04-24
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0649 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/7813
摘要： A vertical type MOSFET and a manufacturing method thereof, in which its drift resistance is made to be low by securing its breakdown voltage between source and drain electrodes of about 150 V being the middle class breakdown voltage and its manufacturing method is easy and its manufacturing cost is low, are provided. At a vertical type MOSFET, in which an N type high resistance drift layer is formed on an N type substrate and P type base layers are formed in designated regions of the surface of the high resistance drift layer and N type source layers are formed in the base layers and gate electrodes are formed on specified regions of the surface of the high resistance drift layer, a trench type back gate section is formed in a trench positioned at a region between the gate electrodes, by filling a insulation material in the trench.
摘要翻译：一种垂直型MOSFET及其制造方法，其中通过将其150V左右的源极和漏极之间的击穿电压确保为中等级击穿电压，使其漂移电阻变低，并且其制造方法容易，并且其制造成本是低的，提供。在N型衬底上形成有N型高电阻漂移层的垂直型MOSFET，在高电阻漂移层的表面的指定区域形成P型基极层，在基极层和栅电极形成在高电阻漂移层的表面的特定区域上，通过在沟槽中填充绝缘材料，在位于栅电极之间的区域中的沟槽中形成沟槽型背栅极部。

5. 发明授权

US07564098B2 Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps 失效
标题翻译：具有沟槽式栅极的半导体器件及其制造方法能够简化制造步骤
公开(公告)号：US07564098B2
公开(公告)日：2009-07-21
申请号：US11798930
申请日：2007-05-17
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4925 , H01L29/511 , H01L29/518 , H01L29/66734
摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.
摘要翻译：在半导体器件中，在半导体晶片的沟槽内形成栅极二氧化硅层。第一栅电极经由栅极二氧化硅层形成在半导体晶片的沟槽的侧壁上。绝缘层经由栅极二氧化硅层形成在半导体晶片的沟槽的底部上并被第一栅电极包围。绝缘层不包括二氧化硅，并且具有与二氧化硅不同的蚀刻特性。第二栅电极被埋在半导体晶片的沟槽中，并与第一栅电极和绝缘层接触。

6. 发明申请

US20070284657A1 Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps 失效
标题翻译：具有沟槽型栅极的半导体器件及其制造方法能够简化制造步骤
公开(公告)号：US20070284657A1
公开(公告)日：2007-12-13
申请号：US11798930
申请日：2007-05-17
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4925 , H01L29/511 , H01L29/518 , H01L29/66734
摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.
摘要翻译：在半导体器件中，在半导体晶片的沟槽内形成栅极二氧化硅层。第一栅电极经由栅极二氧化硅层形成在半导体晶片的沟槽的侧壁上。绝缘层经由栅极二氧化硅层形成在半导体晶片的沟槽的底部上并被第一栅电极包围。绝缘层不包括二氧化硅，并且具有与二氧化硅不同的蚀刻特性。第二栅电极被埋在半导体晶片的沟槽中，并与第一栅电极和绝缘层接触。

7. 发明授权

US5818282A Bridge circuitry comprising series connection of vertical and lateral MOSFETS 失效
标题翻译：桥接电路，包括垂直和横向MOSFET的串联连接
公开(公告)号：US5818282A
公开(公告)日：1998-10-06
申请号：US797313
申请日：1997-02-07
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/78 , H03K17/56
CPC分类号： H01L27/088
摘要： A field relaxation region of the second conductivity type is formed between the base region and a drain electrode contact portion at which the drain region contacts with a drain electrode but distanced from both the base region and the drain electrode contact portion and the field relaxation region is also separated via the drain region from the laterally extending portion of the semiconductor isolation region to form a drain current channel region between the field relaxation region and the laterally extending portion of the semiconductor isolation region and further the field relaxation region is electrically connected via an interconnection to the source region and the vertically extending portion of the semiconductor isolation region so that the field relaxation region and the semiconductor isolation region have the same potential as the source region whereby if the lateral MOS field effect transistor is reverse-biased by a voltage, then a first space charge region is formed which extend from a first p-n junction surface between the laterally extending portion of the semiconductor isolation region and the drain current channel region of the drain region toward the drain current channel region and a second space charge region is formed which extend from a second p-n junction surface between the field relaxation region and the drain current channel region of the drain region toward the drain current channel region for causing the first and second space charge regions to contact with each other to pinch the drain current channel region off.
摘要翻译：第二导电类型的场弛豫区域形成在漏极区域与漏电极接触但是与基极区域和漏电极接触部分两者相隔离的场区域和漏极电极接触部分之间的基极区域和漏电极接触部分之间还经由漏极区域与半导体隔离区域的横向延伸部分分离，以在场弛豫区域和半导体隔离区域的横向延伸部分之间形成漏极电流沟道区域，此外场弛豫区域经由互连到源极区域和半导体隔离区域的垂直延伸部分，使得场弛豫区域和半导体隔离区域具有与源极区域相同的电位，从而如果横向MOS场效应晶体管被电压反向偏置，则形成第一空间电荷区域从半导体隔离区域的横向延伸部分和漏极区域的漏极电流沟道区域之间的第一pn结表面延伸到漏极电流沟道区域，并且形成第二空间电荷区域，其从第二pn结表面延伸，漏极区域的场弛豫区域和漏极电流沟道区域朝向漏极电流沟道区域，以使第一和第二空间电荷区域相互接触以夹紧漏极电流沟道区域。

8. 发明申请

US20090227102A1 Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps 失效
公开(公告)号：US20090227102A1
公开(公告)日：2009-09-10
申请号：US12453551
申请日：2009-05-14
申请人： Wataru Sumida
发明人： Wataru Sumida
IPC分类号： H01L21/3205
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4925 , H01L29/511 , H01L29/518 , H01L29/66734
摘要： In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

9. 发明授权

US06639278B2 Semiconductor device 有权
公开(公告)号：US06639278B2
公开(公告)日：2003-10-28
申请号：US10057642
申请日：2002-01-25
申请人： Wataru Sumida , Michiaki Maruoka , Akihiro Shimomura , Manabu Yamada
发明人： Wataru Sumida , Michiaki Maruoka , Akihiro Shimomura , Manabu Yamada
IPC分类号： H01L31119
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/7811 , H01L29/7813
摘要： At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

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