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1. 发明授权

US5593927A Method for packaging semiconductor dice 失效
标题翻译：封装半导体芯片的方法
公开(公告)号：US5593927A
公开(公告)日：1997-01-14
申请号：US565864
申请日：1995-12-01
申请人： Warren M. Farnworth , Alan G. Wood , Trung T. Doan , John O. Jacobson
发明人： Warren M. Farnworth , Alan G. Wood , Trung T. Doan , John O. Jacobson
IPC分类号： H01L23/29 , H01L23/31 , H01L23/528 , H01L25/065 , H01L29/06 , H01L21/60
CPC分类号： H01L24/48 , H01L23/291 , H01L23/3171 , H01L23/528 , H01L25/0657 , H01L2224/05624 , H01L2224/05647 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2225/06541 , H01L2225/06551 , H01L2225/06575 , H01L2225/06582 , H01L2225/06593 , H01L29/0657 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/14 , H01L2924/181
摘要： A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.
摘要翻译：用于封装半导体管芯的方法包括在管芯上形成附加的保护层和导电迹线。然后将模具放置在具有用于建立与导电迹线的电连接的电连接器的多模保持器中。保护层形成为电绝缘材料如聚合物，玻璃，氮化物或氧化物的薄膜或厚膜。此外，保护层可以形成有锥形的周缘，以便于将模具插入模座。

2. 发明授权

US5585282A Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor 失效
标题翻译：用于在半导体的电气测试的突出接触件上形成凸起部分的工艺
公开(公告)号：US5585282A
公开(公告)日：1996-12-17
申请号：US406637
申请日：1995-03-20
申请人： Alan G. Wood , Trung T. Doan , Warren M. Farnworth , Tim J. Corbett
发明人： Alan G. Wood , Trung T. Doan , Warren M. Farnworth , Tim J. Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , H01L21/28 , H01L21/308
CPC分类号： H05K3/4007 , G01R1/0466 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , G01R3/00 , H01L2224/13012 , H01L2224/13019 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81192 , H01L2224/81345 , H01L2224/83192 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A process for forming die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. In the preferred embodiment, the substrate is formed of semiconductor material, with the raised portions being formed by etching. The arrangement may be used for establishing temporary electrical contact with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
摘要翻译：用于与模具建立欧姆接触的用于形成模具接触衬底的方法在接触构件上形成有凸起部分。凸起部分的尺寸被设计成使得对模具施加到基板上的压缩力导致接触构件有限地渗透到粘合垫中。在优选实施例中，衬底由半导体材料形成，凸起部分通过蚀刻形成。该装置可用于与老化烘箱和分立模具测试仪建立临时电接触。这允许在组装之前对模具进行表征，从而可以以未包装的形式转移模具。 Z轴各向异性导电互连材料可以插入在模具附接表面和模具之间。

3. 发明授权

US06828812B2 Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections 失效
标题翻译：用于测试半导体裸片的测试装置，包括具有用于进行电连接的穿透限制触点的衬底
公开(公告)号：US06828812B2
公开(公告)日：2004-12-07
申请号：US08838452
申请日：1997-04-07
申请人： Warren M. Farnworth , Alan G. Wood , Trung T. Doan , David R. Hembree
发明人： Warren M. Farnworth , Alan G. Wood , Trung T. Doan , David R. Hembree
IPC分类号： G01R1073
CPC分类号： H01L23/49838 , G01R1/0466 , G01R1/0483 , G01R1/0735 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/48 , H01L24/85 , H01L2224/05554 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/81192 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/10161 , H01L2924/14 , H01L2924/15151 , H01L2924/15173 , H01L2924/15174 , H01L2924/15787 , H01L2924/16195 , H05K3/0058 , H05K3/0067 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
摘要翻译：模具接触衬底通过接触构件上的凸起部分与模具建立欧姆接触。凸起部分的尺寸被设计成使得对模具施加到基板上的压缩力导致接触构件有限地渗透到粘合垫中。该装置可用于建立与老化炉的电气接触以及离散的模具测试器。这允许在组装之前对模具进行表征，从而可以以未包装的形式转移模具。 Z轴各向异性导电互连材料可以插入在模具附接表面和模具之间。

4. 发明授权

US06881974B2 Probe card for testing microelectronic components 有权
标题翻译：用于测试微电子元件的探针卡
公开(公告)号：US06881974B2
公开(公告)日：2005-04-19
申请号：US10730548
申请日：2003-12-08
申请人： Alan G. Wood , Trung T. Doan , David R. Hembree
发明人： Alan G. Wood , Trung T. Doan , David R. Hembree
IPC分类号： G01R3/00 , G01R31/28 , H05K3/00 , H05K3/40 , H05K3/42 , H01L23/58 , G01R31/02
CPC分类号： G01R3/00 , G01R31/2886 , H01L2224/05001 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H05K3/002 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09563 , H05K2203/025 , Y10T29/49004 , Y10T29/49153 , Y10T29/49165 , H01L2224/05624 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05155 , H01L2224/05171
摘要： Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.
摘要翻译：本发明的各个方面提供了制造探针卡和测试系统的方法，该测试系统可以使用这种探针卡测试微电子部件。在一个具体示例中，可以通过在基板中形成多个盲孔来制造探针卡，每个孔具有与基板的背面间隔开的背部厚度的封闭底部。可以在衬底上沉积导电金属以填充孔并且在衬底上限定覆盖层。每个孔中的金属可以限定导体。可以去除覆盖层的至少一部分以将每个导体彼此电隔离。去除包括背部厚度的基板的一部分以限定从基板的剩余厚度向外延伸的销的阵列，其中每个销是导体之一的暴露长度。

5. 发明授权

US06773938B2 Probe card, e.g., for testing microelectronic components, and methods for making same 失效
标题翻译：探针卡，例如用于测试微电子部件，以及制造它们的方法
公开(公告)号：US06773938B2
公开(公告)日：2004-08-10
申请号：US10230653
申请日：2002-08-29
申请人： Alan G. Wood , Trung T. Doan , David R. Hembree
发明人： Alan G. Wood , Trung T. Doan , David R. Hembree
IPC分类号： H01L2166
CPC分类号： G01R3/00 , G01R31/2886 , H01L2224/05001 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H05K3/002 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09563 , H05K2203/025 , Y10T29/49004 , Y10T29/49153 , Y10T29/49165 , H01L2224/05624 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05155 , H01L2224/05171
摘要： Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.
摘要翻译：本发明的各个方面提供了制造探针卡和测试系统的方法，该测试系统可以使用这种探针卡测试微电子部件。在一个具体示例中，可以通过在基板中形成多个盲孔来制造探针卡，每个孔具有与基板的背面间隔开的背部厚度的封闭底部。可以在衬底上沉积导电金属以填充孔并且在衬底上限定覆盖层。每个孔中的金属可以限定导体。可以去除覆盖层的至少一部分以将每个导体彼此电隔离。去除包括背部厚度的基板的一部分以限定从基板的剩余厚度向外延伸的销的阵列，其中每个销是导体之一的暴露长度。

6. 发明授权

US08384192B2 Methods for forming small-scale capacitor structures 有权
标题翻译：形成小型电容器结构的方法
公开(公告)号：US08384192B2
公开(公告)日：2013-02-26
申请号：US13047430
申请日：2011-03-14
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , Cem Basceri , David J. Kubista
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与介电层接触并具有不大于约的厚度。

7. 发明授权

US08124491B2 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US08124491B2
公开(公告)日：2012-02-28
申请号：US12547197
申请日：2009-08-25
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

8. 发明申请

US20110284866A1 LIGHT-EMITTING DIODE (LED) STRUCTURE HAVING A WAVELENGTH-CONVERTING LAYER AND METHOD OF PRODUCING 审中-公开
标题翻译：具有波长转换层的发光二极管（LED）结构及其制造方法
公开(公告)号：US20110284866A1
公开(公告)日：2011-11-24
申请号：US13191235
申请日：2011-07-26
申请人： CHUONG A. TRAN , Trung T. Doan , Jui-Kang Yen , Yung-Wei Chen
发明人： CHUONG A. TRAN , Trung T. Doan , Jui-Kang Yen , Yung-Wei Chen
IPC分类号： H01L33/42 , H01L33/40 , H01L33/50
CPC分类号： H01L33/0079 , H01L33/22 , H01L33/44 , H01L33/508 , H01L33/641 , H01L2224/48247 , H01L2224/48257 , H01L2224/8592 , H01L2924/181 , H01L2924/00012
摘要： A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.
摘要翻译：提供了具有用于产生均匀的白光的基本上保形的波长转换层的发光二极管（LED）装置以及在晶片和各个晶片级上制造所述LED的方法。 LED装置包括金属基板，耦合到金属基板的p型半导体，耦合到p型半导体的有源区，耦合到有源区的n型半导体以及耦合到n型半导体的波长转换层型半导体。

9. 发明授权

US07935950B2 Controllable ovonic phase-change semiconductor memory device and methods of programming the same 有权
标题翻译：可控的卵子相变半导体存储器件及其编程方法
公开(公告)号：US07935950B2
公开(公告)日：2011-05-03
申请号：US11833034
申请日：2007-08-02
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L47/00 , H01L29/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的超声相变半导体存储器件及其编程方法。这种存储器件包括包括非平行侧壁的下电极。绝缘材料覆盖下电极，使得下电极的上表面露出。在一个实施例中，绝缘材料和下电极可以具有共面上表面。在另一个实施例中，下电极的上表面在绝缘材料的凹槽内。硫族化物材料和上电极形成在下电极的上表面上。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

10. 发明授权

US07771537B2 Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition 有权
标题翻译：用于在微特征工件加工（例如CVD沉积）期间控制温度的方法和系统
公开(公告)号：US07771537B2
公开(公告)日：2010-08-10
申请号：US11418337
申请日：2006-05-04
申请人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
发明人： Kevin L. Beaman , Trung T. Doan , Lyle D. Breiner , Ronald A. Weimer , Er-Xuan Ping , David J. Kubista , Cem Basceri , Lingyi A. Zheng
IPC分类号： C23C16/00
CPC分类号： C23C16/00 , C23C16/46
摘要： The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.
摘要翻译：本公开提供了用于控制温度的方法和系统。该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。目标温度可以根据斜坡分布来确定，但是一个实现中的控制温度在第一温度和第二温度之间交替。

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