专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06262933B1 High speed programmable address decoder 有权
标题翻译：高速可编程地址解码器
公开(公告)号：US06262933B1
公开(公告)日：2001-07-17
申请号：US09494186
申请日：2000-01-28
申请人： Wanli Chang , David Jefferson
发明人： Wanli Chang , David Jefferson
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.
摘要翻译：高性能地址解码器电路为可编程逻辑集成电路的嵌入式存储器提供更高速度的读和写访问。地址解码器是可编程的，以允许以不同的数据宽度和深度寻址存储器。电路可以用作列地址解码器或行地址解码器，或两者兼有。在存储器的双端口存储器实现中，每个解码器可以有两个实例，一个用于写入，一个用于读取。

2. 发明授权

US06459303B1 High speed programmable address decoder 有权
标题翻译：高速可编程地址解码器
公开(公告)号：US06459303B1
公开(公告)日：2002-10-01
申请号：US09829499
申请日：2001-04-09
申请人： Wanli Chang , David Jefferson
发明人： Wanli Chang , David Jefferson
IPC分类号： H03K19082
CPC分类号： G11C8/10
摘要： A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.
摘要翻译：高性能地址解码器电路为可编程逻辑集成电路的嵌入式存储器提供更高速度的读和写访问。地址解码器是可编程的，以允许以不同的数据宽度和深度寻址存储器。电路可以用作列地址解码器或行地址解码器，或两者兼有。在存储器的双端口存储器实现中，每个解码器可以有两个实例，一个用于写入，一个用于读取。

3. 发明授权

US07818584B1 One-time programmable memories for key storage 有权
标题翻译：用于密钥存储的一次性可编程存储器
公开(公告)号：US07818584B1
公开(公告)日：2010-10-19
申请号：US11042937
申请日：2005-01-25
申请人： Juju Joyce , Martin Langhammer , Keone Streicher , David Jefferson
发明人： Juju Joyce , Martin Langhammer , Keone Streicher , David Jefferson
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F12/1433 , G06F21/76 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.
摘要翻译：存储和防止存储的编码密钥，串行标识号或其他信息的修改或擦除的电路，方法和装置。与本发明的实施例一起存储的编码密钥可用于解码诸如FPGA的集成电路上的配置比特流。序列号可用于跟踪或认证集成电路。本发明的实施例将该信息存储在诸如SRAM，DRAM，EPROM，EEPROM，闪存，熔丝阵列或其它类型的存储器之类的存储器中。为了防止其擦除或修改，存储器的写使能电路然后被永久禁用，并且如果存储器是易失性的，则提供连续的电源。进一步细化验证在允许设备被配置或可操作之前写使能电路已被禁用。

4. 发明授权

US07161381B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07161381B1
公开(公告)日：2007-01-09
申请号：US10787818
申请日：2004-02-25
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

5. 发明授权

US07051153B1 Memory array operating as a shift register 有权
标题翻译：存储器阵列作为移位寄存器
公开(公告)号：US07051153B1
公开(公告)日：2006-05-23
申请号：US10140312
申请日：2002-05-06
申请人： Yi-Wen Lin , Changsong Zhang , David Jefferson , Srinivas Reddy
发明人： Yi-Wen Lin , Changsong Zhang , David Jefferson , Srinivas Reddy
IPC分类号： G06F12/00
CPC分类号： G11C19/38
摘要： A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.
摘要翻译：配置为作为移位寄存器操作的存储器阵列包括具有输入和输出的第一列存储器单元和具有输入和输出的至少第二列存储器单元。存储器阵列还包括连接在第一列存储器单元的输出和第二列存储单元的输入之间的多路复用器。存储器阵列可以通过多路复用器将数据从第一列存储器单元移位到第二列而不是使用一般路由线来作为移位寄存器来操作。

6. 发明授权

US06326812B1 Programmable logic device with logic signal delay compensated clock network 有权
标题翻译：具有逻辑信号延迟补偿时钟网络的可编程逻辑器件
公开(公告)号：US06326812B1
公开(公告)日：2001-12-04
申请号：US09625439
申请日：2000-07-26
申请人： David Jefferson
发明人： David Jefferson
IPC分类号： G06F110
CPC分类号： G06F1/10 , H03K5/13 , H03L7/081 , H03L7/0891 , H03L7/0995 , H03L7/18
摘要： An integrated circuit programmable logic device comprising: a plurality of programmable logic elements that are responsive to clock signals; a clock signal generation circuit which produces a first clock signal; a first phase shifting element which produces a second clock signal which is a phase-shifted version of the first clock signal, shifted in phase by an amount which compensates for a logic signal delay; and a clock signal distribution network which distributes the first and second clock signals among the programmable logic elements.
摘要翻译：一种集成电路可编程逻辑器件，包括：响应于时钟信号的多个可编程逻辑元件; 产生第一时钟信号的时钟信号发生电路; 第一相移元件，其产生第二时钟信号，该第二时钟信号是第一时钟信号的相移版本，相位移位补偿逻辑信号延迟的量; 以及在可编程逻辑元件之间分配第一和第二时钟信号的时钟信号分配网络。

7. 发明授权

US08826038B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08826038B1
公开(公告)日：2014-09-02
申请号：US13474745
申请日：2012-05-18
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： G06F21/00
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

8. 发明授权

US07343470B1 Techniques for sequentially transferring data from a memory device through a parallel interface 有权
标题翻译：用于通过并行接口从存储设备顺序传送数据的技术
公开(公告)号：US07343470B1
公开(公告)日：2008-03-11
申请号：US10673081
申请日：2003-09-26
申请人： Juju Joyce , Dan Mansur , David Jefferson , Changsong Zhang , Yi-Wen Lin
发明人： Juju Joyce , Dan Mansur , David Jefferson , Changsong Zhang , Yi-Wen Lin
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/4243
摘要： Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.
摘要翻译：提供了用于使用顺序读取模式从外部存储器件并行地将数据同步发送到目标电路的技术。存储装置包括地址计数器。地址计数器产生存储在存储器件中的数据位的顺序读地址。目标电路产生一个控制地址计数器的时钟信号。目的地电路还可以将开始地址发送到存储器件。地址计数器响应于以起始地址开始的时钟信号的转变顺序地产生新的读地址。数据位从存储器件并行传输到目标电路。

9. 发明授权

US07228451B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit 有权
标题翻译：可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
公开(公告)号：US07228451B1
公开(公告)日：2007-06-05
申请号：US11270801
申请日：2005-11-08
申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
发明人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
摘要翻译：用于集成电路的时钟网络包括被配置为将时钟信号分配给集成电路的第一部分的第一组线路。时钟网络还包括第二组线路，其被配置为将时钟信号分配给集成电路的第一部分与集成电路的第二部分分开。

10. 发明授权

US06417694B1 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06417694B1
公开(公告)日：2002-07-09
申请号：US09956748
申请日：2001-09-19
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式