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1. 发明授权

US5977793A Programmable logic device with hierarchical interconnection resources 失效
公开(公告)号：US5977793A
公开(公告)日：1999-11-02
申请号：US855192
申请日：1997-05-13
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H01L21/82 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1778
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

2. 发明授权

US06417694B1 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06417694B1
公开(公告)日：2002-07-09
申请号：US09956748
申请日：2001-09-19
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

3. 发明授权

US06798242B2 Programmable logic device with hierarchical interconnection resources 失效
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06798242B2
公开(公告)日：2004-09-28
申请号：US10426991
申请日：2003-04-29
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

4. 发明授权

US06577160B2 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06577160B2
公开(公告)日：2003-06-10
申请号：US10170026
申请日：2002-06-10
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联。本地导体与每个区域相关联。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

5. 发明授权

US06300794B1 Programmable logic device with hierarchical interconnection resources 有权
标题翻译：具有分层互连资源的可编程逻辑器件
公开(公告)号：US06300794B1
公开(公告)日：2001-10-09
申请号：US09488025
申请日：2000-01-20
申请人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
发明人： Srinivas T. Reddy , Richard G. Cliff , Christopher F. Lane , Ketan H. Zaveri , Manuel M. Mejia , David Jefferson , Bruce B. Pedersen , Andy L. Lee
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.
摘要翻译：可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。水平和垂直超超导区域互连导体分别与每行和列相关联。每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。本地导体与每个区域相关联，主要用于使信号进入该区域。在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的也是当地的导体）。水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

6. 发明授权

US06278288B1 Programmable logic device with enhanced multiplexing capabilities in interconnect resources 有权
标题翻译：具有增强的互连资源复用能力的可编程逻辑器件
公开(公告)号：US06278288B1
公开(公告)日：2001-08-21
申请号：US09574371
申请日：2000-05-19
申请人： Andy L. Lee , Richard G. Cliff , David Jefferson , Cameron McClintock , Kurosu R. Altaf
发明人： Andy L. Lee , Richard G. Cliff , David Jefferson , Cameron McClintock , Kurosu R. Altaf
IPC分类号： G06F738
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.
摘要翻译：可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。

7. 发明授权

US6121790A Programmable logic device with enhanced multiplexing capabilities in interconnect resources 失效
标题翻译：具有增强的互连资源复用能力的可编程逻辑器件
公开(公告)号：US6121790A
公开(公告)日：2000-09-19
申请号：US87631
申请日：1998-05-29
申请人： Andy L. Lee , Richard G. Cliff , David Jefferson , Cameron McClintock , Kurosu R. Altaf
发明人： Andy L. Lee , Richard G. Cliff , David Jefferson , Cameron McClintock , Kurosu R. Altaf
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736 , H03K19/1778
摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmably selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.
摘要翻译：可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。在设备上提供的用于将几个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。

8. 发明授权

US07161381B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07161381B1
公开(公告)日：2007-01-09
申请号：US10787818
申请日：2004-02-25
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

9. 发明授权

US06720796B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US06720796B1
公开(公告)日：2004-04-13
申请号：US10140311
申请日：2002-05-06
申请人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
发明人： Srinivas Reddy , David Jefferson , Christopher F. Lane , Vikram Santurkar , Richard Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
摘要翻译：可编程逻辑器件（PLD）包括第一存储器块和至少第二存储器块，其中两个存储器块具有不同的存储器大小。

10. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

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