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1. 发明申请

US20100171187A1 FORMATION OF HIGH-K GATE STACKS IN SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件中形成高K栅极堆叠
公开(公告)号：US20100171187A1
公开(公告)日：2010-07-08
申请号：US12637787
申请日：2009-12-15
申请人： Wanda Andreoni , Alessandro Curioni , Carlo A. Pignedoli
发明人： Wanda Andreoni , Alessandro Curioni , Carlo A. Pignedoli
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28194 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517
摘要： A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.
摘要翻译：形成用于MOSFET器件的高K栅极堆叠以控制MOSFET器件的阈值电压的方法。第一高K金属氧化物层形成在半导体衬底上。然后在第一层上直接形成至少一个复合层。复合层由直接形成在偶极感应层上的第二高K金属氧化物层组成。偶极子诱导层包括具有比第一和第二层更高的氧空位亲和力和更低的氧空位扩散率的高K金属氧化物。然后在复合层上形成金属栅电极。各层的形成使得将复合层的偶极子感应层定位在栅电极和衬底之间，以将阈值电压移动到期望的水平。还提供了通过上述方法形成的MOSFET器件中的高K栅极堆叠。

2. 发明授权

US08273618B2 Formation of high-K gate stacks in semiconductor devices 有权
标题翻译：在半导体器件中形成高K栅极叠层
公开(公告)号：US08273618B2
公开(公告)日：2012-09-25
申请号：US12637787
申请日：2009-12-15
申请人： Wanda Andreoni , Alessandro Curioni , Carlo A. Pignedoli
发明人： Wanda Andreoni , Alessandro Curioni , Carlo A. Pignedoli
IPC分类号： H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517
摘要： A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.
摘要翻译：形成用于MOSFET器件的高K栅极堆叠以控制MOSFET器件的阈值电压的方法。第一高K金属氧化物层形成在半导体衬底上。然后在第一层上直接形成至少一个复合层。复合层由直接形成在偶极感应层上的第二高K金属氧化物层组成。偶极子诱导层包括具有比第一和第二层更高的氧空位亲和力和更低的氧空位扩散率的高K金属氧化物。然后在复合层上形成金属栅电极。各层的形成使得将复合层的偶极子感应层定位在栅电极和衬底之间，以将阈值电压移动到期望的水平。还提供了通过上述方法形成的MOSFET器件中的高K栅极堆叠。

3. 发明申请

US20080293259A1 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY 有权
标题翻译：形成具有高移动性的金属/高k栅极堆叠的方法
公开(公告)号：US20080293259A1
公开(公告)日：2008-11-27
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
IPC分类号： H01L21/263
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

4. 发明授权

US07115959B2 Method of forming metal/high-k gate stacks with high mobility 有权
公开(公告)号：US07115959B2
公开(公告)日：2006-10-03
申请号：US10873733
申请日：2004-06-22
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evengi Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph P. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evengi Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph P. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

5. 发明授权

US08153514B2 Method of forming metal/high-κ gate stacks with high mobility 有权
标题翻译：金属/高分子金属成型方法移动性高的门栈
公开(公告)号：US08153514B2
公开(公告)日：2012-04-10
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L21/3205
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

6. 发明申请

US20120216862A1 Silicon: Hydrogen Photovoltaic Devices, Such As Solar Cells, Having Reduced Light Induced Degradation And Method Of Making Such Devices 有权
标题翻译：硅：氢光伏器件，如太阳能电池，减少光诱导的降解和制造这些器件的方法
公开(公告)号：US20120216862A1
公开(公告)日：2012-08-30
申请号：US13036584
申请日：2011-02-28
申请人： Ahmed Abou-Kandil , Nasser Afify , Wanda Andreoni , Alessandro Curioni , Augustin J. Hong , Jeehwan Kim , Petr Khomyakov , Devendra K. Sadana
发明人： Ahmed Abou-Kandil , Nasser Afify , Wanda Andreoni , Alessandro Curioni , Augustin J. Hong , Jeehwan Kim , Petr Khomyakov , Devendra K. Sadana
IPC分类号： H01L31/0264 , H01L31/0376 , H01L31/20
CPC分类号： H01L31/202 , C23C16/24 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02658 , H01L31/0376 , H01L31/03926 , H01L31/075 , Y02E10/548 , Y02P70/521
摘要： A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device.
摘要翻译：制造光伏器件的方法包括提供用于光伏器件的可拉伸衬底; 并拉伸基底以产生拉伸的基底。该方法还包括将包含氢化非晶硅的结构沉积在拉伸的基底上; 以及对沉积的氢化非晶硅结构和拉伸的基底进行压缩力以形成压缩应变光伏器件。

7. 发明申请

US20050280105A1 Method of forming metal/high-k gate stacks with high mobility 有权
标题翻译：形成高迁移率的金属/高k栅极叠层的方法
公开(公告)号：US20050280105A1
公开(公告)日：2005-12-22
申请号：US10873733
申请日：2004-06-22
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/84 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低，或更大。

8. 发明授权

US08927857B2 Silicon: hydrogen photovoltaic devices, such as solar cells, having reduced light induced degradation and method of making such devices 有权
标题翻译：硅：诸如太阳能电池的氢光伏器件具有降低的光诱导劣化和制造这种器件的方法
公开(公告)号：US08927857B2
公开(公告)日：2015-01-06
申请号：US13036584
申请日：2011-02-28
申请人： Ahmed Abou-Kandil , Nasser Afify , Wanda Andreoni , Alessandro Curioni , Augustin J. Hong , Jeehwan Kim , Petr Khomyakov , Devendra K. Sadana
发明人： Ahmed Abou-Kandil , Nasser Afify , Wanda Andreoni , Alessandro Curioni , Augustin J. Hong , Jeehwan Kim , Petr Khomyakov , Devendra K. Sadana
IPC分类号： H01L31/20 , H01L31/0392 , H01L21/02 , H01L31/0376 , H01L31/075 , C23C16/24
CPC分类号： H01L31/202 , C23C16/24 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02658 , H01L31/0376 , H01L31/03926 , H01L31/075 , Y02E10/548 , Y02P70/521
摘要： A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device.
摘要翻译：制造光伏器件的方法包括提供用于光伏器件的可拉伸衬底; 并拉伸基底以产生拉伸的基底。该方法还包括将包含氢化非晶硅的结构沉积在拉伸的基底上; 以及对沉积的氢化非晶硅结构和拉伸的基底进行压缩力以形成压缩应变光伏器件。

9. 发明申请

US20060289903A1 Method of forming metal/high-k gate stacks with high mobility 审中-公开
标题翻译：形成高迁移率的金属/高k栅极叠层的方法
公开(公告)号：US20060289903A1
公开(公告)日：2006-12-28
申请号：US11513101
申请日：2006-08-30
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L31/112 , H01L29/80
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解，或更大。

10. 发明授权

US07057244B2 Dielectric materials 失效
标题翻译：介电材料
公开(公告)号：US07057244B2
公开(公告)日：2006-06-06
申请号：US10624021
申请日：2003-07-21
申请人： Wanda Andreoni , Alessandro Curioni , Stephen A. Shevlin
发明人： Wanda Andreoni , Alessandro Curioni , Stephen A. Shevlin
IPC分类号： H01L29/76
CPC分类号： H01L21/02197 , C23C14/08 , C30B23/02 , C30B29/22 , H01L21/02269 , H01L21/28167 , H01L21/31604 , H01L21/31616 , H01L29/517
摘要： An article of manufacture comprises a substrate and a layer of N(x)Y(1−x)AlO3 on the substrate where x is a molar fraction greater than zero and less than one, and N is an element selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The article may be an electronic device further comprising an electrode electrically isolated from the substrate by the layer. In particular, the dielectric properties of the layer are such that the layer is especially although by no means exclusively useful for electrically isolating gate electrodes in field effect transistor devices. The layer may be formed on the substrate via molecular beam epitaxy.
摘要翻译：一种制品包括在基底上的基底和一层N（x）Y（1-x）3 Al 3/3，其中x是大于零且小于1的摩尔分数，N是选自La，Ce，Pr，Nd，Pm，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb和Lu中的元素。物品可以是还包括通过该层与衬底电隔离的电极的电子器件。特别地，该层的介电特性使得该层特别是尽管绝对不能用于场效应晶体管器件中的电绝缘栅电极。层可以通过分子束外延形成在衬底上。

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