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1. 发明申请

US20060289903A1 Method of forming metal/high-k gate stacks with high mobility 审中-公开
标题翻译：形成高迁移率的金属/高k栅极叠层的方法
公开(公告)号：US20060289903A1
公开(公告)日：2006-12-28
申请号：US11513101
申请日：2006-08-30
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evgeni Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L31/112 , H01L29/80
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解，或更大。

2. 发明申请

US20050280105A1 Method of forming metal/high-k gate stacks with high mobility 有权
标题翻译：形成高迁移率的金属/高k栅极叠层的方法
公开(公告)号：US20050280105A1
公开(公告)日：2005-12-22
申请号：US10873733
申请日：2004-06-22
申请人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
发明人： Wanda Andreoni , Alessandro Callegari , Eduard Cartier , Alessandro Curioni , Christopher D'Emic , Evengi Gousev , Michael Gribelyuk , Paul Jamison , Rajarao Jammy , Dianne Lacey , Fenton McFeely , Vijay Narayanan , Carlo Pignedoli , Joseph Shepard , Sufi Zafar
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/84 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低，或更大。

3. 发明申请

US20050023664A1 High density chip carrier with integrated passive devices 有权
标题翻译：具有集成无源器件的高密度芯片载体
公开(公告)号：US20050023664A1
公开(公告)日：2005-02-03
申请号：US10930304
申请日：2004-08-31
申请人： Michael Chudzik , Robert Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph Shepard , Anna Wanda Topol
发明人： Michael Chudzik , Robert Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph Shepard , Anna Wanda Topol
IPC分类号： H01L23/12 , H01L23/50 , H01L25/04 , H01L25/18 , H01L29/40 , H05K1/16 , H05K3/46 , H01L21/44 , H01L23/02 , H01L23/52
CPC分类号： H05K1/162 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/157 , H01L2924/30105 , H05K1/167 , H05K3/4602 , H05K2201/09809
摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.
摘要翻译：提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。无源组件包括去耦组件，例如电容器和电阻器。一组连接被集成以提供与受支持的部件的紧密的电气接近。

4. 发明申请

US20070128859A1 Combined Stepper And Deposition Tool 有权
标题翻译：组合步进和沉积工具
公开(公告)号：US20070128859A1
公开(公告)日：2007-06-07
申请号：US11164684
申请日：2005-12-01
申请人： Michael Chudzik , Joseph Shepard
发明人： Michael Chudzik , Joseph Shepard
IPC分类号： H01L21/4763 , H01L21/44 , C23C16/00
CPC分类号： G03F7/168 , G03F7/0035
摘要： A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.
摘要翻译：步进机与在形成集成电路的过程中沉积材料层的硬件结合在一起，从而执行沉积，图案化和清洁，而不会将晶片暴露于工具之间的转移并结合复合工具中的三种工具的功能。通过施加UV光通过步进器的掩模去除图案限定材料，从而消除现有技术方法的烘烤和显影步骤。类似地，UV的泛滥暴露消除了现有技术方法的清洁步骤。

5. 发明申请

US20050059238A1 Cooling system for a semiconductor device and method of fabricating same 有权
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20050059238A1
公开(公告)日：2005-03-17
申请号：US10661299
申请日：2003-09-12
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H01L21/44 , H01L21/48 , H01L23/367
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

6. 发明申请

US20060035393A1 METHODS FOR THE DETERMINATION OF FILM CONTINUITY AND GROWTH MODES IN THIN DIELECTRIC FILMS 失效
标题翻译：薄膜电泳膜中膜连续性和生长模式的测定方法
公开(公告)号：US20060035393A1
公开(公告)日：2006-02-16
申请号：US10710947
申请日：2004-08-13
申请人： Michael Chudzik , Joseph Shepard
发明人： Michael Chudzik , Joseph Shepard
IPC分类号： H01L21/66
CPC分类号： H01L21/02263 , C23C16/45525 , C23C16/52 , H01L21/0228 , H01L21/314
摘要： The invention provides methods for determining film continuity and growth modes in thin dielectric films. The continuity determining method comprises: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison.
摘要翻译：本发明提供了确定薄介电膜中的膜连续性和生长模式的方法。连续性确定方法包括：使用生长度量的第一值将材料沉积在衬底上; 在所述材料的表面上沉积一定量的电荷; 重复地测量材料的表面电压，直到隧道开始，以提供Vtunnel（或Etunnel）值; 对生长度量的不同值重复上述步骤; 以及比较生长度量值的不同值的Vtunnel（或Etunnel）值，以提供衬底上材料的连续性的量度。材料的生长模式可以通过比较Vtunnel或Etunnel的每个生长度量曲线的一阶导数与生长指标，并检查比较结果的线性来确定。

7. 发明申请

US20070064395A1 COOLING SYSTEM FOR A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME 失效
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20070064395A1
公开(公告)日：2007-03-22
申请号：US11558032
申请日：2006-11-09
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H05K7/20 , F28F7/00
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate includes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

8. 发明申请

US20060099815A1 Cooling system for a semiconductor device and method of fabricating same 失效
标题翻译：一种用于半导体器件的冷却系统及其制造方法
公开(公告)号：US20060099815A1
公开(公告)日：2006-05-11
申请号：US11317298
申请日：2005-12-23
申请人： Howard Chen , Louis Hsu , Joseph Shepard
发明人： Howard Chen , Louis Hsu , Joseph Shepard
IPC分类号： H01L21/302
CPC分类号： H01L23/473 , H01L21/4871 , H01L23/3677 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05548 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.
摘要翻译：用于半导体衬底的冷却系统包括由半导体衬底的背面形成的多个沟槽和沉积在多个沟槽中的导热材料。一种在半导体衬底中形成冷却元件的方法，包括用第一掩模层涂覆半导体衬底的背面，在第一掩模层中形成多个沟槽图案，蚀刻半导体衬底以形成沿着多个的多个沟槽的沟槽图案，并且在多个沟槽中沉积导热材料。从晶片背面构成的沟槽提高了从集成电路芯片的正面到背面的传热效率。从晶片的背面制造沟槽允许沟槽的深度和数量的增加，并且提供了将被动和主动的冷却装置直接附接到晶片的背面的手段。

9. 发明申请

US20050266652A1 HIGH DENSITY MIMCAP WITH A UNIT REPEATABLE STRUCTURE 失效
标题翻译：具有单位重复结构的高密度MIMCAP
公开(公告)号：US20050266652A1
公开(公告)日：2005-12-01
申请号：US10709768
申请日：2004-05-27
申请人： Michael Chudzik , Louis Hsu , Joseph Shepard , William Tonti
发明人： Michael Chudzik , Louis Hsu , Joseph Shepard , William Tonti
IPC分类号： H01L21/02 , H01L21/8242 , H01L23/522
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译：用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

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