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1. 发明授权

US4893271A Synthesized clock microcomputer with power saving 失效
标题翻译：合成时钟微电脑，省电
公开(公告)号：US4893271A
公开(公告)日：1990-01-09
申请号：US18761
申请日：1987-02-26
申请人： Walter L. Davis , Barry W. Herold , Wendell L. Little
发明人： Walter L. Davis , Barry W. Herold , Wendell L. Little
IPC分类号： G06F1/08 , G06F1/32 , H03L7/089 , H03L7/107 , H03L7/183
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , H03L7/107 , H03L7/183 , H03L7/0898 , Y02B60/1217
摘要： A microcomputer having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the requirements change, the synthesizer responds to provide only the frequency required. Thus, the power dissipated by the microcomputer system is minimized.
摘要翻译：具有预定时钟脉冲频率要求的微型计算机从乘法型频率合成器接收脉冲，该乘法器利用小于预定要求的最大值的参考频率。合成器响应于程序指令以产生足以满足立即执行编程任务的要求的时钟脉冲频率。随着要求的变化，合成器响应仅提供所需的频率。因此，微机系统耗散的功率被最小化。

2. 发明授权

US4749991A Turn off protection circuit 失效
标题翻译：关闭保护电路
公开(公告)号：US4749991A
公开(公告)日：1988-06-07
申请号：US054079
申请日：1987-05-21
申请人： Walter L. Davis , Wendell L. Little , Barry W. Herold
发明人： Walter L. Davis , Wendell L. Little , Barry W. Herold
IPC分类号： G08B3/10 , H04B1/16 , H04Q1/00
CPC分类号： G08B3/1066 , H04W52/0283
摘要： In system capable of self turn-off, a circuit arrangement for providing a controlled turn-off includes a detecting circuit for detecting actuation of a turn-off switch, thereby providing a turn-off authorization signal. A turn-off protection circuit is coupled to the detecting circuit and a controller is coupled to the turn-off protect circuit and the detecting circuit. The controller disables the turn-off protect circuit when the turn-off authorization is received and present. The controller generates a turn-off signal for powering the system down after the turn-off protect circuit has been disabled.
摘要翻译：在能够自我关闭的系统中，用于提供受控关断的电路装置包括用于检测关断开关的致动的检测电路，从而提供关断授权信号。关断保护电路耦合到检测电路，并且控制器耦合到关断保护电路和检测电路。当接收到关闭授权并存在时，控制器禁用关断保护电路。关闭保护电路被禁用后，控制器产生一个关闭信号，用于向系统供电。

3. 发明授权

US5644743A Hybrid analog-digital phase error detector 失效
标题翻译：混合模拟数字相位误差检测器
公开(公告)号：US5644743A
公开(公告)日：1997-07-01
申请号：US567387
申请日：1995-12-04
申请人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
发明人： Raymond Louis Barrett, Jr. , Barry W. Herold , Grazyna Anna Pajunen , Walter L. Davis
IPC分类号： H03D13/00 , H03L7/087 , H03D3/24
CPC分类号： H03L7/087 , H03D13/00
摘要： A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.
摘要翻译：混合模拟数字相位误差检测器（107）用于检测第一和第二时钟信号（132,104）之间的相位误差。数字和模拟相位误差检测器（108,116）连接到第一和第二时钟信号（132,104），并用于产生数字和模拟相位误差值（110,118）。连接到数字和模拟相位误差检测器（108,116）的数字和模拟控制器（112,120）基于数字和模拟相位误差值（110,118）执行数字和模拟控制算法，以产生数字和模拟控制信号（114,122）。连接到数字和模拟控制器（112,120）的输出的加法器（124）组合模拟控制信号（122）和数字控制信号（114）以产生表示相位误差的复合控制信号（126）。

4. 发明授权

US5122778A Serial word comparator 失效
标题翻译：串行字比较器
公开(公告)号：US5122778A
公开(公告)日：1992-06-16
申请号：US679811
申请日：1991-03-28
申请人： Richard A. Erhart , Walter L. Davis , Barry W. Herold
发明人： Richard A. Erhart , Walter L. Davis , Barry W. Herold
IPC分类号： G06F7/02 , G06F11/00 , H04W88/02
CPC分类号： H04W88/026 , G06F11/0763 , G06F7/02 , G06F2207/025
摘要： An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal each time a mismatch occurs. These signals are applied directly to an error counter and, after inversion, to a match counter. The contents of the error counter and match counter are compared to a stored threshold number. A first signal is generated if the contents of the error counter exceeds the threshold. A second signal is generated if the contents of the match counter exceeds the threshold. Upon the occurrence of both signals, the serial comparison process is terminated.
摘要翻译：一种用于确定接收的二进制字是否对应于所存储的二进制字的真实或补充版本的装置包括用于将每个二进制字的比特串行复用到异或门的输入的装置。每当发生不匹配时，异或门产生逻辑高电平信号。这些信号直接应用于错误计数器，并在反转后应用于匹配计数器。将错误计数器和匹配计数器的内容与存储的阈值进行比较。如果错误计数器的内容超过阈值，则生成第一个信号。如果匹配计数器的内容超过阈值，则产生第二个信号。发生两个信号时，串行比较处理结束。

5. 发明授权

US4527131A Oscillating circuit exhibiting tolerance to crystal impedance variations 失效
标题翻译：具有耐晶体阻抗变化的振荡电路
公开(公告)号：US4527131A
公开(公告)日：1985-07-02
申请号：US564597
申请日：1983-12-22
申请人： Barry W. Herold , Walter L. Davis
发明人： Barry W. Herold , Walter L. Davis
IPC分类号： H03B5/36
CPC分类号： H03B5/364
摘要： An MOS crystal controlled oscillator circuit is provided which includes a pair of MOS transistors coupled together in complementary fashion to form a first non-inverting stage. The output of the first non-inverting stage is coupled to the input of a second non-inverting stage including a MOS transistor exhibiting a source follower configuration or a bipolar transistor exhibiting an emitter follower configuration. The output of the second non-inverting source follower stage is coupled via a feedback element, for example, a piezoelectric crystal, to the input of the first non-inverting stage. A feedback loop is thus formed which causes the circuit to resonate at a frequency determined by the piezoelectric crystal feedback device. This oscillator configuration results in a degree of insensitivity to variations in parasitic impedance of the piezoelectric crystal feedback device. That is, the oscillator remains operative on the desired resonant frequency despite significant variations in the parasitic impedance associated with the piezoelectric crystal element.
摘要翻译：提供一种MOS晶体振荡器电路，其包括以互补方式耦合在一起的一对MOS晶体管，以形成第一非反相级。第一非反相级的输出耦合到包括呈现源极跟随器配置的MOS晶体管或呈现射极跟随器配置的双极晶体管的第二非反相级的输入端。第二非反相源极跟随器级的输出通过反馈元件（例如压电晶体）耦合到第一非反相级的输入端。由此形成反馈回路，使得电路以由压电晶体反馈装置确定的频率谐振。该振荡器配置导致对压电晶体反馈装置的寄生阻抗的变化的不敏感度。也就是说，尽管与压电晶体元件相关联的寄生阻抗存在显着变化，振荡器保持在期望谐振频率上的操作。

6. 发明授权

US5058204A Synthesized selective call receiver having variable characteristics 失效
标题翻译：具有可变特性的综合选呼接收机
公开(公告)号：US5058204A
公开(公告)日：1991-10-15
申请号：US551669
申请日：1990-07-13
申请人： Omid Tahernia , Walter L. Davis , Barry W. Herold
发明人： Omid Tahernia , Walter L. Davis , Barry W. Herold
IPC分类号： H03J5/02
CPC分类号： H03J5/0281
摘要： A paging receiver has a synthesizer for governing the receive frequency. The paging receiving further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth of a loop filter within a phase lock loop within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.
摘要翻译：寻呼接收机具有用于控制接收频率的合成器。寻呼接收还具有响应于接收频率而变化的特性。这些特征包括改变合成器内的锁相环内的环路滤波器的带宽，以及改变用于从恢复的音频信号提取DC电平的检测器电路被禁用的时间。此外，环路滤波器的带宽响应于从第一接收频率切换到第二接收频率而变化，以提供均匀的频率锁定时间或快速频率锁定时间。此外，检测器电路被禁用的时间相应地改变。

7. 发明授权

US4901036A Frequency synthesizer with an interface controller and buffer memory 失效
标题翻译：具有接口控制器和缓冲存储器的频率合成器
公开(公告)号：US4901036A
公开(公告)日：1990-02-13
申请号：US372997
申请日：1989-06-29
申请人： Barry W. Herold , Omid Tahernia , Walter L. Davis , Mario A. Rivas
发明人： Barry W. Herold , Omid Tahernia , Walter L. Davis , Mario A. Rivas
IPC分类号： H03L7/18 , H03J5/02
CPC分类号： H03J5/0281
摘要： A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
摘要翻译：具有至少一个可编程表征的锁相环电路的频率合成器包括缓冲存储器和响应于从中央控制器接收的操作代码的接口控制器，用于引导用于在所述至少一个锁相环电路，缓冲存储器和中央控制器。在一个实施例中，数据字在中央控制器和锁相环电路或缓冲存储器之间的传送是根据预先指定的协议进行的，并由中央控制器产生的时钟信号来执行。缓冲存储器与至少一个锁相环电路之间的数据字传输也可以根据预先指定的协议进行串行执行，但也可以由频率合成器产生的内部时钟信号自主地进行控制。

8. 发明授权

US5392452A Selective call signaling system with combined wide area paging and high data rate transmissions via radio telephone transceivers 失效
标题翻译：选择性呼叫信令系统，通过无线电话收发器进行组合广域寻呼和高数据速率传输
公开(公告)号：US5392452A
公开(公告)日：1995-02-21
申请号：US982341
申请日：1992-11-27
申请人： Walter L. Davis
发明人： Walter L. Davis
IPC分类号： H04B5/00 , H04W84/02 , H04B7/00
CPC分类号： H04W84/022
摘要： A cooperative paging system (10) and radio telephone system (15) combine to provide conventional delivery of short paging messages to a combination pager/radio telephone (40) via a first communication path, while a radio telephone link operating at a higher data rate is used to deliver large data messages to the pager/radio telephone (40). The radio telephone link is formed by a transceiver section (205) of the pager/radio telephone (40) coupling to a radio telephone base station (50,52) and calling up a paging terminal (32) of the paging system (10). The paging terminal (32) retrieves the large data messages from a temporary message memory (42) to deliver to the pager/radio telephone (40).
摘要翻译：合作寻呼系统（10）和无线电话系统（15）组合以经由第一通信路径向组合寻呼机/无线电话（40）提供短寻呼消息的常规传送，而以更高数据速率操作的无线电话链路用于向寻呼机/无线电话机（40）发送大量数据消息。无线电话链路由耦合到无线电话基站（50,52）并呼叫寻呼系统（10）的寻呼终端（32）的寻呼机/无线电话机（40）的收发机部分（205）形成，。寻呼终端（32）从临时消息存储器（42）检索大数据消息以传送到寻呼机/无线电话机（40）。

9. 发明授权

US5251325A Battery saving method and apparatus for providing selective receiver power switching 失效
标题翻译：提供选择性接收机功率切换的节电方法和装置
公开(公告)号：US5251325A
公开(公告)日：1993-10-05
申请号：US532844
申请日：1990-06-04
申请人： Walter L. Davis , James G. Mittel
发明人： Walter L. Davis , James G. Mittel
IPC分类号： H04B1/16 , H04W52/02 , H04W88/02 , H04Q3/02 , H04B7/00
CPC分类号： H04B1/1615 , H04W52/0283 , H04W88/022
摘要： A battery saving apparatus selectively supplies power to each receiver function of a battery powered communication receiver at predetermined time intervals prior to and continuing therefrom for enabling the reception of the coded message signals with each receiver function being powered only as long as is required for each receiver function to stabilize prior to the reception of the coded message signals.
摘要翻译：蓄电池节省装置在电池供电的通信接收机的每个接收机功能之前以预定的时间间隔选择性地向其提供电力，从而使得能够接收每个接收机功能的编码消息信号，只要每个接收机所需的时间长用于在接收编码的消息信号之前稳定。

10. 发明授权

US5117500A Multi system decoding receiver 失效
标题翻译：多系统解码接收机
公开(公告)号：US5117500A
公开(公告)日：1992-05-26
申请号：US83743
申请日：1988-03-30
申请人： Walter L. Davis , Kuppuswamy Raghunathan
发明人： Walter L. Davis , Kuppuswamy Raghunathan
IPC分类号： G08B3/10 , H04B1/16 , H04B5/04 , H04L7/033 , H04L7/04 , H04W8/24 , H04W88/02
CPC分类号： G08B3/1066 , H04W52/0232 , H04W8/245 , H04W88/026 , H04L7/0337 , H04L7/042 , H04W88/022
摘要： A battery powered receiver including a adaptive signal decoder is disclosed which is capable of processing detected encoded signals in accordance with a plurality of decoding schemes. The decoder has an equivalent microcomputer implementation. Energy conservation means operating independently of the detected signals acts to conserve the energy of the battery.
摘要翻译：公开了一种包括自适应信号解码器的电池供电的接收机，其能够根据多种解码方案来处理检测到的编码信号。解码器具有等效的微处理器实现。节能意味着独立于检测到的信号工作，以节省电池的能量。

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