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1. 发明申请

US20130094273A1 3D MEMORY AND DECODING TECHNOLOGIES 审中-公开
标题翻译： 3D存储和解码技术
公开(公告)号：US20130094273A1
公开(公告)日：2013-04-18
申请号：US13706001
申请日：2012-12-05
申请人： WEI-CHIH CHIEN , MING-HSIU LEE , HSIANG-LAN LUNG
发明人： WEI-CHIH CHIEN , MING-HSIU LEE , HSIANG-LAN LUNG
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/249 , H01L28/24 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/1633
摘要： A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.
摘要翻译： 3D存储器件基于导电柱阵列和多个图案化的导体平面，其包括在左侧和右侧界面区域处邻近导电柱的左侧和右侧导体。左侧和右侧界面区域中的存储元件包括可以通过内置自切换行为表征的可编程过渡金属氧化物或其它可编程电阻材料。可以使用二维解码来选择导电柱，并且可以使用与左侧和右侧选择相结合的第三维度上的解码来选择多个平面中的左侧和右侧导体。

2. 发明申请

US20120231613A1 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE 有权
标题翻译： 3D内存阵列安排FN隧道程序和删除
公开(公告)号：US20120231613A1
公开(公告)日：2012-09-13
申请号：US13476964
申请日：2012-05-21
申请人： HSIANG-LAN LUNG , YEN-HAO SHIH , ERH-KUN LAI , MING HSIU LEE , HANG-TING LUE
发明人： HSIANG-LAN LUNG , YEN-HAO SHIH , ERH-KUN LAI , MING HSIU LEE , HANG-TING LUE
IPC分类号： H01L21/20
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

3. 发明申请

US20110286283A1 3D TWO-BIT-PER-CELL NAND FLASH MEMORY 有权
标题翻译： 3D双比特单片NAND闪存
公开(公告)号：US20110286283A1
公开(公告)日：2011-11-24
申请号：US12785291
申请日：2010-05-21
申请人： HSIANG-LAN LUNG , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming Hsiu Lee , Tien-Yen Wang
发明人： HSIANG-LAN LUNG , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/04 , H01L21/336
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译：描述了一种3D存储器件，其包括具有垂直NAND串结构的相应阵列的底部和顶部存储器立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

4. 发明申请

US20100265773A1 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE 有权
标题翻译： 3D内存阵列安排FN隧道程序和删除
公开(公告)号：US20100265773A1
公开(公告)日：2010-10-21
申请号：US12705158
申请日：2010-02-12
申请人： HSIANG-LAN LUNG , Yen-Hao Shih , Erh-Kun Lai , Ming Hsiu Lee , Hang-Ting Lue
发明人： HSIANG-LAN LUNG , Yen-Hao Shih , Erh-Kun Lai , Ming Hsiu Lee , Hang-Ting Lue
IPC分类号： G11C16/04 , H01L21/76
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

5. 发明申请

US20110317480A1 PHASE CHANGE MEMORY CODING 有权
标题翻译：相变存储器编码
公开(公告)号：US20110317480A1
公开(公告)日：2011-12-29
申请号：US12823508
申请日：2010-06-25
申请人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
发明人： HSIANG-LAN LUNG , Ming Hsiu Lee , Yen-Hao Shih , Tien-Yen Wang , Chao-I Wu
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0092
摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.
摘要翻译：集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。在对数据集进行编码之后，将集成电路相变存储器安装在基板上。在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

6. 发明申请

US20110049456A1 PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY 审中-公开
标题翻译：用于相变记忆的复合掺杂相变结构
公开(公告)号：US20110049456A1
公开(公告)日：2011-03-03
申请号：US12553784
申请日：2009-09-03
申请人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
发明人： HSIANG-LAN LUNG , CHIEH-FANG CHEN , YEN-HAO SHIH , HUAI-YU CHENG , ERH-KUN LAI , MING HSIU LEE , MATTHEW J. BREITWISCH , SIMONE RAO , CHUNG HON LAM
IPC分类号： H01L45/00 , H01L21/06
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1641
摘要： A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region.
摘要翻译：使用在第一电极和第二电极之间的复合掺杂相变材料来描述存储器件。相变材料的存储元件，例如硫族化物，位于第一和第二电极之间并且具有有源区。相变材料具有第一掺杂剂，例如氧化硅，其特征在于倾向于在有源区域中的晶界上与相变材料分离，并且具有第二掺杂剂，例如硅，其特征在于引起再结晶温度的增加的和/或抑制活性区域中的相变材料中的空隙形成。

7. 发明申请

US20090236639A1 STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY 有权
标题翻译：堆叠位线双字线非易失性存储器
公开(公告)号：US20090236639A1
公开(公告)日：2009-09-24
申请号：US12475839
申请日：2009-06-01
申请人： HSIANG-LAN LUNG
发明人： HSIANG-LAN LUNG
IPC分类号： H01L29/66
CPC分类号： H01L27/11206 , H01L21/76895 , H01L23/50 , H01L23/5252 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
摘要翻译：一种非易失性存储器件的布置，其具有至少一个在半导体衬底上层次级别堆叠的存储器件级，每个存储器级包括基本上设置在半导体衬底之上的氧化物层，基本上设置在氧化物层上方的多条字线; 基本上设置在所述氧化物层上方的多个位线; 基本上与字线电接触的多个通孔插塞和基本上设置在位线旁边的侧壁上且与多个位线侧壁反熔丝电介质基本上接触的抗熔丝电介质材料。

8. 发明申请

US20120181599A1 LOW COST SCALABLE 3D MEMORY 有权
标题翻译：低成本可扩展3D内存
公开(公告)号：US20120181599A1
公开(公告)日：2012-07-19
申请号：US13070323
申请日：2011-03-23
申请人： HSIANG-LAN LUNG
发明人： HSIANG-LAN LUNG
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.
摘要翻译：描述了一种集成电路装置，其包括3D存储器，该3D存储器包括多个自对准堆叠的字线，其与多个自对准堆叠的位线正交并交错。诸如介电电荷存储结构之类的数据存储结构被提供在与多条自对准堆叠的位线交错的字线的多个自对齐堆叠中的字线和位线之间的交叉点处。

9. 发明申请

US20110084397A1 3D INTEGRATED CIRCUIT LAYER INTERCONNECT 有权
标题翻译： 3D集成电路层互连
公开(公告)号：US20110084397A1
公开(公告)日：2011-04-14
申请号：US12579192
申请日：2009-10-14
申请人： HSIANG-LAN LUNG
发明人： HSIANG-LAN LUNG
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/522 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/11206 , H01L27/11286 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.
摘要翻译：描述了具有小占地面积的三维3D互连结构，其用于从多层设备中的上述电路结构层次的连接。另外，提供了用于制造3D互连结构的有效且低成本的方法。

10. 发明申请

US20110013446A1 REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY 有权
标题翻译：刷新电路相位变化记忆
公开(公告)号：US20110013446A1
公开(公告)日：2011-01-20
申请号：US12503566
申请日：2009-07-15
申请人： HSIANG-LAN LUNG
发明人： HSIANG-LAN LUNG
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0033 , G11C13/004 , G11C16/3431
摘要： A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.
摘要翻译：如本文所述的存储器件包括相变存储器单元的参考阵列和相变存储器单元的存储器阵列，其中存储在参考阵列中的当前数据集与预期数据集之间的差用于确定何时刷新内存阵列。用于参考阵列的高电阻状态是具有比用于存储器阵列的高电阻状态的最小电阻的最小电阻的“部分复位”状态。感测电路适于读取参考阵列的存储器单元，并且如果存储在参考阵列中的当前数据集与预期数据组之间存在差异，则产生刷新命令信号，以及响应于刷新命令信号的控制电路对存储器阵列的存储单元执行刷新操作。

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