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1. 发明申请

US20100291735A1 STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS 审中-公开
标题翻译：包含预制TRENCH INTERCONNECT VIAS的可堆叠半导体芯片层
公开(公告)号：US20100291735A1
公开(公告)日：2010-11-18
申请号：US12844555
申请日：2010-07-27
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L21/70 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

2. 发明授权

US07786562B2 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias 有权
标题翻译：可堆叠半导体芯片层，包括预制沟槽互连通孔
公开(公告)号：US07786562B2
公开(公告)日：2010-08-31
申请号：US11150712
申请日：2005-06-10
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L23/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

3. 发明申请

US20050277288A1 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias 有权
标题翻译：可堆叠半导体芯片层，包括预制沟槽互连通孔
公开(公告)号：US20050277288A1
公开(公告)日：2005-12-15
申请号：US11150712
申请日：2005-06-10
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

4. 发明授权

US09431275B2 Wire bond through-via structure and method 有权
标题翻译：引线键合通孔结构和方法
公开(公告)号：US09431275B2
公开(公告)日：2016-08-30
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
IPC分类号： H01L23/488 , H01L21/56 , H01L23/00 , H01L25/10
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

5. 发明授权

US07239012B2 Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers 有权
标题翻译：由包含具有上覆互连层的IC芯片的层组成的三维模块
公开(公告)号：US07239012B2
公开(公告)日：2007-07-03
申请号：US10951990
申请日：2004-09-28
申请人： Angel Pepe , James Yamaguchi
发明人： Angel Pepe , James Yamaguchi
IPC分类号： H01L23/02 , H01L23/58 , H01L23/48
CPC分类号： H01L21/568 , H01L21/6835 , H01L22/32 , H01L23/3121 , H01L23/5388 , H01L25/105 , H01L2221/68359 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2225/1023 , H01L2225/1064 , H01L2924/1433 , H01L2924/18161
摘要： A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages. Each layer is bonded to form a stack of integrated circuit containing layers.
摘要翻译：公开了一种由层形成的预先形成的集成电路芯片的模块。每个层包含通过与预先形成的集成电路芯片分开形成互连组件而封装在电子封装中的集成电路芯片。如果互连组件测试良好，则它连接到准备好的集成电路芯片。互连组件被翻转接合到芯片。互连组件和芯片被钝化或封装成整体结构以提供电子封装。在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。然后将集成电路芯片变薄。访问测试板来测试芯片。多个互连组件和芯片结合在一起以形成相应的多个电子封装。每个层被结合以形成包含层的集成电路的堆叠。

6. 发明申请

US20050037540A1 Three-dimensional module comprised of layers containing IC chips with overlying interconnect layers and a method of making the same 有权
标题翻译：由包含具有上覆互连层的IC芯片的层构成的三维模块及其制造方法
公开(公告)号：US20050037540A1
公开(公告)日：2005-02-17
申请号：US10951990
申请日：2004-09-28
申请人： Angel Pepe , James Yamaguchi
发明人： Angel Pepe , James Yamaguchi
IPC分类号： H01L21/68 , H01L23/31 , H01L23/538 , H01L23/58 , H01L21/44 , H01L21/48
CPC分类号： H01L21/568 , H01L21/6835 , H01L22/32 , H01L23/3121 , H01L23/5388 , H01L25/105 , H01L2221/68359 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2225/1023 , H01L2225/1064 , H01L2924/1433 , H01L2924/18161
摘要： A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.
摘要翻译：通过与预先形成的集成电路芯片分开形成互连组件，预先形成的集成电路芯片被封装到电子封装中。如果互连组件测试良好，则它连接到准备好的集成电路芯片。互连组件被翻转接合到芯片。互连组件和芯片被钝化或封装成整体结构以提供电子封装。在互连层中限定至少一个测试焊盘，该测试焊盘可以被访问并电连接在测试焊盘的相对侧上。芯片底部填充有绝缘材料，以去除芯片和互连组件之间的所有空隙。然后将集成电路芯片变薄。访问测试板来测试芯片。多个互连组件和芯片结合在一起以形成相应的多个电子封装。

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