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1. 发明授权

US09431275B2 Wire bond through-via structure and method 有权
标题翻译：引线键合通孔结构和方法
公开(公告)号：US09431275B2
公开(公告)日：2016-08-30
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
IPC分类号： H01L23/488 , H01L21/56 , H01L23/00 , H01L25/10
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

2. 发明申请

US20120068333A1 Wire Bond Through-Via Structure and Method 有权
标题翻译：电线键合通孔结构和方法
公开(公告)号：US20120068333A1
公开(公告)日：2012-03-22
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

3. 发明申请

US20120069528A1 Method for Control of Solder Collapse in Stacked Microelectronic Structure 审中-公开
标题翻译：堆叠微电子结构焊接塌陷控制方法
公开(公告)号：US20120069528A1
公开(公告)日：2012-03-22
申请号：US13209933
申请日：2011-08-15
申请人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
发明人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
IPC分类号： H05K7/00 , B23K1/20
CPC分类号： B23K1/0016 , B23K1/20 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/15331
摘要： A process and product made from the process is disclosed to minimize solder collapse during solder reflow.Predetermined bond pads on a layer or component have a solder paste such as Sn63 solder paste with a first lower reflow temperature applied and a spacer element such as an SAC solder ball or stud bump having a predetermined geometry with a second higher reflow temperature applied. The SAC solder balls or stud bumps act as spacing elements but do not interact with the solder paste such that the solder paste may be reflowed while precisely maintaining the space between the layers.
摘要翻译：公开了由该方法制成的工艺和产品，以使焊料回流期间的焊料塌陷最小化。层或部件上的预定接合焊盘具有焊膏，例如施加第一较低回流温度的Sn63焊膏，以及施加具有第二较高回流温度的具有预定几何形状的间隔元件，例如SAC焊球或螺柱凸块。 SAC焊球或螺柱凸起用作间隔元件，但不与焊膏相互作用，使得焊膏可以在精确地保持层之间的空间的同时回流焊。

4. 发明授权

US08637985B2 Anti-tamper wrapper interconnect method and a device 有权
标题翻译：防篡改包装互连方法和设备
公开(公告)号：US08637985B2
公开(公告)日：2014-01-28
申请号：US13370381
申请日：2012-02-10
申请人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
发明人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
IPC分类号： H01L23/488
CPC分类号： H01L23/57 , H01L24/17 , H05K1/0275 , H05K3/321 , H05K3/4015
摘要： A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.
摘要翻译：一种使用引线接合设备和由该方法制造的器件将防篡改网电连接到电子模块或设备的方法。螺柱凸起或自由气球接合电耦合到防篡改网的导电网垫。相应的模块焊盘具有设置在其上的导电环氧树脂，用于接收柱形凸块或自由空气球接合，每个凸起对准并结合在一起以将防篡改网电耦合到预定的模块焊盘。

5. 发明申请

US20120211886A1 Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the Method 审中-公开
标题翻译：用于制造小型脚印芯片级封装的方法和由该方法制成的器件
公开(公告)号：US20120211886A1
公开(公告)日：2012-08-23
申请号：US13399051
申请日：2012-02-17
申请人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
发明人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L24/96 , H01L21/561 , H01L21/568 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/97 , H01L2924/18162 , H01L2224/19
摘要： A method for fabricating an integrated circuit chip-scale package and a device made from the method. One or more IC chips are mounted on a carrier and a stud bump defined on an IC pad. The stud-bumped IC is encapsulated to define a potted assembly layer which is thinned to expose the stud bump. Conductive first traces are defined and coupled to the stud bump to reroute the IC pads. A dielectric layer is provided and vias defined there through to expose the first traces. Electrically conductive second traces are disposed on the dielectric layer surface that are coupled to the first traces to reroute the IC pads to define a chip scale package.
摘要翻译：一种用于制造集成电路芯片级封装的方法和由该方法制成的器件。一个或多个IC芯片安装在载体上，并且固定在IC垫上。螺柱凸起的IC被封装以限定一个盆形组件层，其被变薄以暴露螺柱凸块。导电的第一迹线被定义并耦合到螺柱凸块以重新路由IC焊盘。提供介电层，并在其中限定通孔以露出第一迹线。导电的第二迹线设置在电介质层表面上，其耦合到第一迹线以重新路由IC焊盘以限定芯片级封装。

6. 发明授权

US08609473B2 Method for fabricating a neo-layer using stud bumped bare die 有权
标题翻译：使用螺柱冲压裸露模制造新层的方法
公开(公告)号：US08609473B2
公开(公告)日：2013-12-17
申请号：US13271797
申请日：2011-10-12
申请人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
发明人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L24/05 , H01L25/105 , H01L2224/02313 , H01L2224/02333 , H01L2224/02379 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2225/1035 , H01L2225/1064 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
摘要翻译：公开了一种用于制造可堆叠集成电路层的方法和由该方法制成的器件。在集成电路管芯的接触焊盘上限定了一个螺栓凸块，并且该螺柱凸块被封装在灌封材料中以限定一个盆组件。去除灌封材料的预定部分，从而露出柱形凸块的一部分。一个或多个导电迹线被限定在层表面上并且与柱形凸起电连接以将集成电路触点重新路由到该层上的预定位置以提供可堆叠的新层。

7. 发明申请

US20120068336A1 Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die 有权
标题翻译：使用螺柱冲压裸模制造新层的方法
公开(公告)号：US20120068336A1
公开(公告)日：2012-03-22
申请号：US13271797
申请日：2011-10-12
申请人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
发明人： Peter Lieu , James Yamaguchi , Randy Bindrup , W. Eric Boyd
IPC分类号： H01L29/12 , H01L21/56
CPC分类号： H01L21/568 , H01L24/05 , H01L25/105 , H01L2224/02313 , H01L2224/02333 , H01L2224/02379 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2225/1035 , H01L2225/1064 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.
摘要翻译：公开了一种用于制造可堆叠集成电路层的方法和由该方法制成的器件。在集成电路管芯的接触焊盘上限定了一个螺栓凸块，并且该螺柱凸块被封装在灌封材料中以限定一个盆组件。去除灌封材料的预定部分，从而露出柱形凸块的一部分。一个或多个导电迹线被限定在层表面上并且与柱形凸起电连接以将集成电路触点重新路由到该层上的预定位置以提供可堆叠的新层。

8. 发明申请

US20120205801A1 Anti-Tamper Wrapper Interconnect Method and a Device 有权
标题翻译：防篡改包裹互连方法和设备
公开(公告)号：US20120205801A1
公开(公告)日：2012-08-16
申请号：US13370381
申请日：2012-02-10
申请人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
发明人： Randy Bindrup , James Yamaguchi , W. Eric Boyd
IPC分类号： H01L23/498 , B32B37/12
CPC分类号： H01L23/57 , H01L24/17 , H05K1/0275 , H05K3/321 , H05K3/4015
摘要： A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads.
摘要翻译：一种使用引线接合设备和由该方法制造的器件将防篡改网电连接到电子模块或设备的方法。螺柱凸起或自由气球接合电耦合到防篡改网的导电网垫。相应的模块焊盘具有设置在其上的导电环氧树脂，用于接收柱形凸块或自由空气球接合，每个凸起对准并结合在一起以将防篡改网电耦合到预定的模块焊盘。

9. 发明申请

US20110085304A1 Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias 审中-公开
标题翻译：热管理装置包括具有电隔离通孔的导热散热器
公开(公告)号：US20110085304A1
公开(公告)日：2011-04-14
申请号：US12925147
申请日：2010-10-13
申请人： Randy Bindrup , Michael Miyake
发明人： Randy Bindrup , Michael Miyake
IPC分类号： H05K7/20 , F28F7/00 , B21D53/02 , H05K13/00
CPC分类号： H01L23/49833 , H01L21/4871 , H01L23/36 , H01L23/3677 , H01L23/4006 , H01L23/49827 , H01L25/03 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , H01L2924/15311 , Y10T29/4935
摘要： A thermally conductive heat spreader is disclosed comprising one or more electrically isolated through-hole vias to provide, for instance, one or more thermal management layers having one or more electrically insulated and electrically conductive through-hole vias in a microelectronic module for the rerouting of one or more electrical signals to one or more layers in a stack of integrated circuit chip layers.The method of the invention comprises disposing an electrically conductive member within an aperture in a heat spreader blank wherein the electrically conductive member is electrically insulated from the heat spreader blank by means of a dielectric layer to provide a vertical through-hole via for the vertical routing of an electrical signal through the heat spreader.
摘要翻译：公开了一种导热散热器，其包括一个或多个电隔离的通孔通孔，以提供例如在微电子模块中具有一个或多个电绝缘和导电通孔通孔的一个或多个热管理层，用于重新布线一个或多个电信号到集成电路芯片层堆叠中的一个或多个层。本发明的方法包括将导电构件设置在散热器坯料的孔内，其中导电构件借助于电介质层与散热器坯件电绝缘，以提供用于垂直布线的垂直通孔通孔的电信号通过散热器。

10. 发明申请

US20050271320A1 Low-loss optical waveguide crossovers using an out-of-plane waveguide 失效
标题翻译：使用平面外波导的低损耗光波导交叉
公开(公告)号：US20050271320A1
公开(公告)日：2005-12-08
申请号：US11202675
申请日：2005-08-12
申请人： Arthur Telkamp , Randy Bindrup
发明人： Arthur Telkamp , Randy Bindrup
IPC分类号： G02B6/12 , G02B6/125 , G02B6/136
CPC分类号： G02B6/125 , G02B6/12002 , G02B6/136 , G02B2006/12145 , G02B2006/12147
摘要： An improved low-loss waveguide crossover uses an out-of-plane, such as vertical, waveguide to bridge over any number of waveguides with very low, or essentially no, optical loss or crosstalk. Optical signals transmitted in a waveguide system having the improved waveguide crossover can cross over one or multiple transverse waveguides with a greatly reduced loss of signal intensity by using a second waveguide (such as a bridge) positioned in a second plane different from the plane containing the transverse waveguides. An optical signal from the input waveguide is coupled efficiently through directional coupling to the bridge waveguide and optionally from the bridge waveguide to the output waveguide. Methods for fabricating the improved waveguide crossover are described.
摘要翻译：改进的低损耗波导交叉使用诸如垂直波导的平面外的桥接在任何数量的波导上，具有非常低或基本上没有的光损耗或串扰。在具有改进的波导交叉的波导系统中传输的光信号可以跨越一个或多个横向波导，通过使用位于不同于包含第二波导的平面的第二平面中的第二波导（例如桥），信号强度的损失大大降低横向波导。来自输入波导的光信号通过定向耦合到桥式波导并且可选地从桥式波导到输出波导有效地耦合。描述了制造改进的波导交叉的方法。

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