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1. 发明申请

US20110072119A1 Accelerated Cable Modem Restart Service 有权
标题翻译：加速电缆调制解调器重启服务
公开(公告)号：US20110072119A1
公开(公告)日：2011-03-24
申请号：US12566581
申请日：2009-09-24
申请人： Vladimir Bronstein , James Chen , Xiaogang Zhu , Tienchuan Ko
发明人： Vladimir Bronstein , James Chen , Xiaogang Zhu , Tienchuan Ko
IPC分类号： G06F15/177 , G06F15/16
CPC分类号： H04L41/0889 , H04L41/046 , H04L41/082 , H04L41/0843
摘要： A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided. The system includes: a memory; and a caching entity configured to monitor transmissions from the provisioning server of the configuration files to the network nodes so as to both store the configurations files in the memory and to pass-through the configuration files to the network nodes; the caching entity being further configured to monitor requests to the provisioning server for respective ones of the DOCSIS configuration files from the network nodes, the caching entity being further configured to determine for each of the requests whether the requested configuration file has been previously requested node such that if the caching entity determines that the requested configuration file has been previously requested the caching entity retrieves the previously requested configuration file from the memory and returns the retrieved-from-memory configuration file to the network node.
摘要翻译：提供了一种用于通过DOCSIS配置服务器和根据DOCSIS配置文件配置的多个网络节点之间的有线服务接口规范（DOCSIS）配置文件来加速重新提供数据的系统。系统包括：内存; 以及缓存实体，被配置为监视从配置服务器向配置文件发送到网络节点，以便将配置文件存储在存储器中并将配置文件传递到网络节点; 所述缓存实体还被配置为监视来自所述网络节点的所述DOCSIS配置文件中的相应文件的对所述配置服务器的请求，所述缓存实体还被配置为针对所请求的每个请求确定所请求的配置文件是否已经被先前请求的节点如果缓存实体确定先前请求了所请求的配置文件，则缓存实体从存储器检索先前请求的配置文件，并将从内存中配置文件检索到网络节点。

2. 发明授权

US08489717B2 Accelerated cable modem restart service 有权
标题翻译：加速电缆调制解调器重启服务
公开(公告)号：US08489717B2
公开(公告)日：2013-07-16
申请号：US12566581
申请日：2009-09-24
申请人： Vladimir Bronstein , James Chen , Xiaogang Zhu , Tienchuan Ko
发明人： Vladimir Bronstein , James Chen , Xiaogang Zhu , Tienchuan Ko
IPC分类号： G06F15/177
CPC分类号： H04L41/0889 , H04L41/046 , H04L41/082 , H04L41/0843
摘要： A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided. The system includes: a memory; and a caching entity configured to monitor transmissions from the provisioning server of the configuration files to the network nodes so as to both store the configurations files in the memory and to pass-through the configuration files to the network nodes; the caching entity being further configured to monitor requests to the provisioning server for respective ones of the DOCSIS configuration files from the network nodes, the caching entity being further configured to determine for each of the requests whether the requested configuration file has been previously requested node such that if the caching entity determines that the requested configuration file has been previously requested the caching entity retrieves the previously requested configuration file from the memory and returns the retrieved-from-memory configuration file to the network node.
摘要翻译：提供了一种用于通过DOCSIS配置服务器和根据DOCSIS配置文件配置的多个网络节点之间的有线服务接口规范（DOCSIS）配置文件来加速重新提供数据的系统。系统包括：内存; 以及缓存实体，被配置为监视从配置服务器向配置文件发送到网络节点，以便将配置文件存储在存储器中并将配置文件传递到网络节点; 所述缓存实体还被配置为监视来自所述网络节点的所述DOCSIS配置文件中的相应文件的对所述配置服务器的请求，所述缓存实体还被配置为针对所请求的每个请求确定所请求的配置文件是否已经被先前请求的节点如果缓存实体确定先前请求了所请求的配置文件，则缓存实体从存储器检索先前请求的配置文件，并将从内存中配置文件检索到网络节点。

3. 发明申请

US20050060621A1 Method and system for direct access memory testing of an integrated circuit 失效
标题翻译：用于集成电路直接存取存储器测试的方法和系统
公开(公告)号：US20050060621A1
公开(公告)日：2005-03-17
申请号：US10940146
申请日：2004-09-13
申请人： Jonathan Lee , Xiaogang Zhu , Andrew Hwang
发明人： Jonathan Lee , Xiaogang Zhu , Andrew Hwang
IPC分类号： G11C29/48 , G11C29/00
CPC分类号： G11C29/48 , G11C2029/0401
摘要： Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
摘要翻译：可以在用于测试集成电路的方法和系统中找到本发明的方面，并且可以包括地址选择器，数据选择器和耦合到信号发生器的分级寄存器。地址选择器可以包括直接访问存储器测试（DAMT）模式地址控制输入和耦合到被测嵌入式存储器件（DUT）的一个或多个输出地址引脚。数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚，并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。包括其输入时钟速率四分之一（¼）的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。

4. 发明授权

US08176370B2 Method and system for direct access memory testing of an integrated circuit 失效
标题翻译：用于集成电路直接存取存储器测试的方法和系统
公开(公告)号：US08176370B2
公开(公告)日：2012-05-08
申请号：US10940146
申请日：2004-09-13
申请人： Jonathan Lee , Xiaogang Zhu , Andrew S. Hwang
发明人： Jonathan Lee , Xiaogang Zhu , Andrew S. Hwang
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C2029/0401
摘要： Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
摘要翻译：可以在用于测试集成电路的方法和系统中找到本发明的方面，并且可以包括地址选择器，数据选择器和耦合到信号发生器的分级寄存器。地址选择器可以包括直接访问存储器测试（DAMT）模式地址控制输入和耦合到被测嵌入式存储器件（DUT）的一个或多个输出地址引脚。数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚，并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。包括其输入时钟速率四分之一（¼）的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。

5. 发明申请

US20100005231A1 METHOD AND SYSTEM FOR HARDWARE IMPLEMENTATION OF RESETTING AN EXTERNAL TWO-WIRED EEPROM 有权
标题翻译：用于复位外部二线EEPROM的硬件实现方法和系统
公开(公告)号：US20100005231A1
公开(公告)日：2010-01-07
申请号：US12558803
申请日：2009-09-14
申请人： Jonathan F. Lee , Xiaogang Zhu
发明人： Jonathan F. Lee , Xiaogang Zhu
IPC分类号： G06F12/02 , G06F1/04
CPC分类号： G11C16/16
摘要： Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.
摘要翻译：本文描述了用于电可擦除可编程只读存储器（EEPROM）的硬件控制的方法和系统。本发明的方面可以包括以适于EEPROM操作的频率产生时钟信号，并且利用所生成的时钟信号和硬件产生的数据信号来复位EEPROM而不会由中央处理单元（CPU）启动。复位可能通过虚拟CPU进行。 CPU和虚拟CPU可以集成在单个芯片上。信号产生和EEPROM复位可能通过集成在有限状态机内的虚拟CPU进行。频率计数器可用于从具有比EEPROM所要求的频率更高的频率的时钟源产生时钟信号。

6. 发明授权

US07610456B2 Automatically detecting types of external data flash devices 有权
标题翻译：自动检测外部数据闪存设备的类型
公开(公告)号：US07610456B2
公开(公告)日：2009-10-27
申请号：US11945128
申请日：2007-11-26
申请人： Xiaogang Zhu , Jonathan F. Lee
发明人： Xiaogang Zhu , Jonathan F. Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.
摘要翻译：用于识别设备的方法可以包括由一个或多个存储器设备接收多个读取存储器设备ID命令中的一个或多个。所述一个或多个存储器设备可响应所接收的多个读取存储器设备ID命令中的一个或多个。响应可以包括对应于一个或多个存储器设备的标识信息。多个读取存储器设备ID命令中的一个或多个可以对应于多个被支持的存储器设备中的一个或多个。如果所述响应将所述一个或多个存储器设备标识为所述多个被支持的存储器设备中的一个或多个存储器设备中的一个，则至少一个访问协议可以用于执行对所述一个或多个存储器设备的读取，擦除和/或写入。

7. 发明授权

US07610439B2 Method and system for hardware implementation of resetting an external two-wired EEPROM 有权
标题翻译：复位外部双线EEPROM的硬件实现方法和系统
公开(公告)号：US07610439B2
公开(公告)日：2009-10-27
申请号：US11673348
申请日：2007-02-09
申请人： Jonathan F. Lee , Xiaogang Zhu
发明人： Jonathan F. Lee , Xiaogang Zhu
IPC分类号： G06F1/04
CPC分类号： G11C16/16
摘要： Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.
摘要翻译：本文描述了用于电可擦除可编程只读存储器（EEPROM）的硬件控制的方法和系统。本发明的方面可以包括以适合于EEPROM操作的频率产生时钟信号，并且利用所产生的时钟信号和硬件产生的数据信号来复位EEPROM，而无需来自中央处理单元（CPU）的介入。复位可能通过虚拟CPU进行。本发明的另一方面可以具有通过集成在有限状态机内的虚拟CPU发生信号产生和EEPROM复位。频率计数器可用于从具有比EEPROM所要求的频率更高的频率的时钟源产生时钟信号。

8. 发明授权

US07305528B2 Automatically detecting types of external data flash devices 失效
标题翻译：自动检测外部数据闪存设备的类型
公开(公告)号：US07305528B2
公开(公告)日：2007-12-04
申请号：US11181547
申请日：2005-07-14
申请人： Xiaogang Zhu , Jonathan F. Lee
发明人： Xiaogang Zhu , Jonathan F. Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： Automatically detecting types of external FLASH devices is provided, and may comprise communicating one or more read memory device ID commands corresponding to at least one supported memory device to at least one memory device. Data received in response to this communication may be utilized to determine whether the received data identifies the memory device as one of the plurality of supported memory devices. The supported memory devices may be serial FLASH memory devices. Each read memory device ID command may be manufacturer specific, or may be specific to a group of the supported memory devices. The communicating of read memory device ID commands and determining whether the memory device is a supported memory device may be repeated if the memory device is not identified as one of the supported memory devices. There may be a limit to the number of times this is repeated.
摘要翻译：提供了自动检测外部FLASH设备的类型，并且可以包括将对应于至少一个支持的存储器设备的一个或多个读取存储器设备ID命令传送到至少一个存储器设备。响应于该通信接收的数据可以用于确定接收的数据是否将存储器设备识别为多个被支持的存储器件之一。所支持的存储器件可以是串行FLASH存储器件。每个读取存储器设备ID命令可以是制造商特定的，或者可以是一组所支持的存储器件的特定的。如果存储器设备未被识别为所支持的存储器件之一，则可以重复读取存储器件ID命令的通信并确定存储器件是否是受支持的存储器件。重复次数可能会有限制。

9. 发明申请

US20080195883A1 METHOD AND SYSTEM FOR HARDWARE IMPLEMENTATION OF RESETTING AN EXTERNAL TWO-WIRED EEPROM 有权
标题翻译：用于复位外部二线EEPROM的硬件实现方法和系统
公开(公告)号：US20080195883A1
公开(公告)日：2008-08-14
申请号：US11673348
申请日：2007-02-09
申请人： Jonathan F. Lee , Xiaogang Zhu
发明人： Jonathan F. Lee , Xiaogang Zhu
IPC分类号： G06F1/04 , G06F12/02
CPC分类号： G11C16/16
摘要： Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.
摘要翻译：本文描述了用于电可擦除可编程只读存储器（EEPROM）的硬件控制的方法和系统。本发明的方面可以包括以适合于EEPROM操作的频率产生时钟信号，并且利用所产生的时钟信号和硬件产生的数据信号来复位EEPROM，而无需来自中央处理单元（CPU）的介入。复位可能通过虚拟CPU进行。本发明的另一方面可以具有通过集成在有限状态机内的虚拟CPU发生信号产生和EEPROM复位。频率计数器可用于从具有比EEPROM所要求的频率更高的频率的时钟源产生时钟信号。

10. 发明申请

US20080071979A1 AUTOMATICALLY DETECTING TYPES OF EXTERNAL DATA FLASH DEVICES 有权
标题翻译：自动检测外部数据闪存设备的类型
公开(公告)号：US20080071979A1
公开(公告)日：2008-03-20
申请号：US11945128
申请日：2007-11-26
申请人： Xiaogang Zhu , Jonathan Lee
发明人： Xiaogang Zhu , Jonathan Lee
IPC分类号： G06F12/02 , G06F13/12
CPC分类号： G06F13/4239
摘要： Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.
摘要翻译：用于识别设备的方法可以包括由一个或多个存储器设备接收多个读取存储器设备ID命令中的一个或多个。所述一个或多个存储器设备可响应所接收的多个读取存储器设备ID命令中的一个或多个。响应可以包括对应于一个或多个存储器设备的标识信息。多个读取存储器设备ID命令中的一个或多个可以对应于多个被支持的存储器设备中的一个或多个。如果所述响应将所述一个或多个存储器设备标识为所述多个被支持的存储器设备中的一个或多个存储器设备中的一个，则至少一个访问协议可以用于执行对所述一个或多个存储器设备的读取，擦除和/或写入。

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