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    • 1. 发明申请
    • Method and system for direct access memory testing of an integrated circuit
    • 用于集成电路直接存取存储器测试的方法和系统
    • US20050060621A1
    • 2005-03-17
    • US10940146
    • 2004-09-13
    • Jonathan LeeXiaogang ZhuAndrew Hwang
    • Jonathan LeeXiaogang ZhuAndrew Hwang
    • G11C29/48G11C29/00
    • G11C29/48G11C2029/0401
    • Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
    • 可以在用于测试集成电路的方法和系统中找到本发明的方面,并且可以包括地址选择器,数据选择器和耦合到信号发生器的分级寄存器。 地址选择器可以包括直接访问存储器测试(DAMT)模式地址控制输入和耦合到被测嵌入式存储器件(DUT)的一个或多个输出地址引脚。 数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚,并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。 包括其输入时钟速率四分之一(¼)的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。
    • 3. 发明授权
    • Method and system for direct access memory testing of an integrated circuit
    • 用于集成电路直接存取存储器测试的方法和系统
    • US08176370B2
    • 2012-05-08
    • US10940146
    • 2004-09-13
    • Jonathan LeeXiaogang ZhuAndrew S. Hwang
    • Jonathan LeeXiaogang ZhuAndrew S. Hwang
    • G11C29/00
    • G11C29/48G11C2029/0401
    • Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
    • 可以在用于测试集成电路的方法和系统中找到本发明的方面,并且可以包括地址选择器,数据选择器和耦合到信号发生器的分级寄存器。 地址选择器可以包括直接访问存储器测试(DAMT)模式地址控制输入和耦合到被测嵌入式存储器件(DUT)的一个或多个输出地址引脚。 数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚,并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。 包括其输入时钟速率四分之一(¼)的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。
    • 4. 发明申请
    • AUTOMATICALLY DETECTING TYPES OF EXTERNAL DATA FLASH DEVICES
    • 自动检测外部数据闪存设备的类型
    • US20080071979A1
    • 2008-03-20
    • US11945128
    • 2007-11-26
    • Xiaogang ZhuJonathan Lee
    • Xiaogang ZhuJonathan Lee
    • G06F12/02G06F13/12
    • G06F13/4239
    • Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.
    • 用于识别设备的方法可以包括由一个或多个存储器设备接收多个读取存储器设备ID命令中的一个或多个。 所述一个或多个存储器设备可响应所接收的多个读取存储器设备ID命令中的一个或多个。 响应可以包括对应于一个或多个存储器设备的标识信息。 多个读取存储器设备ID命令中的一个或多个可以对应于多个被支持的存储器设备中的一个或多个。 如果所述响应将所述一个或多个存储器设备标识为所述多个被支持的存储器设备中的一个或多个存储器设备中的一个,则至少一个访问协议可以用于执行对所述一个或多个存储器设备的读取,擦除和/或写入 。
    • 10. 发明申请
    • SYSTEM AND METHOD FOR OSGi-BASED SERVICE DELIVERY FRAMEWORK
    • 基于OSGI的服务交付框架的系统和方法
    • US20110145382A1
    • 2011-06-16
    • US12788272
    • 2010-05-26
    • Jonathan LeePing-Feng WangShin-Jie Lee
    • Jonathan LeePing-Feng WangShin-Jie Lee
    • G06F15/173G06F15/16
    • G06F8/61
    • A system and a method for OBSi-based (open service gateway initiative) service delivery framework are provided. The system is adaptable to a first host executing an OSGi bundle. A mobile service module of the first host is inherited through the OSGi bundle. A second host is assigned when the OSGi bundle calls a mobilize function inherited from the mobile service module. A bytecode and an instance of the OSGi bundle are obtained through a first delivery context processing module of the first host. The bytecode and instance of the OSGi bundle are transmitted from the first host to the second host through the first delivery context processing module and a second delivery context processing module of the second host. The bytecode and instance of the OSGi bundle are installed and the OSGi bundle is executed through the second delivery context processing module.
    • 提供了一种用于基于OBSi(开放服务网关主动)服务交付框架的系统和方法。 该系统适用于执行OSGi包的第一台主机。 第一个主机的移动服务模块通过OSGi包继承。 当OSGi包调用从移动服务模块继承的动员功能时,会分配第二个主机。 通过第一主机的第一传送上下文处理模块获得OSGi包的字节码和实例。 OSGi束的字节码和实例通过第一传送上下文处理模块和第二主机的第二传送上下文处理模块从第一主机传输到第二主机。 安装了OSGi捆绑包的字节码和实例,并通过第二个传递上下文处理模块执行OSGi捆绑包。