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1. 发明授权

US08599053B2 Switched-capacitance gain amplifier with improved input impedance 有权
标题翻译：开关电容增益放大器具有改进的输入阻抗
公开(公告)号：US08599053B2
公开(公告)日：2013-12-03
申请号：US13325248
申请日：2011-12-14
申请人： Vincent Quiquempoix , Philippe Deval , Fabien Vaucher
发明人： Vincent Quiquempoix , Philippe Deval , Fabien Vaucher
IPC分类号： H03M3/00
CPC分类号： H03F3/005 , H03F2200/81 , H03M3/342
摘要： A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having first and second outputs coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier.
摘要翻译：增益放大器可以具有带反馈电容器的差分放大器; 开关输入级具有与差分放大器耦合的第一和第二输出，并具有：第一和第二电容器，接收差分输入信号的第一信号的第一输入; 接收差分输入信号的第二信号的第二输入; 第一多个开关，由第一时钟信号控制，分别将第一电容器的第一端子与第一或第二输入端相连，并分别将第二电容器的第一端子与第二和第一输入端连接; 以及由相移时钟信号控制的第二多个开关，以将第一电容器的第二端子与差分放大器的第一或第二输入端连接，并将第二电容器的第二端子与差分放大器的第二或第一输入端放大器

2. 发明申请

US20120161994A1 SWITCHED-CAPACITANCE GAIN AMPLIFIER WITH IMPROVED INPUT IMPEDANCE 有权
标题翻译：具有改进输入阻抗的开关电容增益放大器
公开(公告)号：US20120161994A1
公开(公告)日：2012-06-28
申请号：US13325248
申请日：2011-12-14
申请人： Vincent Quiquempoix , Philippe Deval , Fabien Vaucher
发明人： Vincent Quiquempoix , Philippe Deval , Fabien Vaucher
IPC分类号： H03M3/04 , H03F3/45
CPC分类号： H03F3/005 , H03F2200/81 , H03M3/342
摘要： A gain amplifier may have a differential amplifier with feedback capacitors; a switched input stage having first and second outputs coupled with the differential amplifier, and having: first and second capacitors, a first input receiving a first signal of a differential input signal; a second input receiving a second signal of the differential input signal; a first plurality of switches controlled by a first clock signal to connect the first terminals of the first capacitor with the first or second input, respectively and to connect the first terminals of the second capacitors with the second and first input, respectively; and a second plurality of switches controlled by a phase shifted clock signal to connect the second terminal of the first capacitor with a first or second input of the differential amplifier and connecting the second terminal of the second capacitor with the second or first input of the differential amplifier.
摘要翻译：增益放大器可以具有带反馈电容器的差分放大器; 开关输入级具有与差分放大器耦合的第一和第二输出，并具有：第一和第二电容器，接收差分输入信号的第一信号的第一输入; 接收差分输入信号的第二信号的第二输入; 第一多个开关，由第一时钟信号控制，分别将第一电容器的第一端子与第一或第二输入端相连，并分别将第二电容器的第一端子与第二和第一输入端连接; 以及由相移时钟信号控制的第二多个开关，以将第一电容器的第二端子与差分放大器的第一或第二输入端连接，并将第二电容器的第二端子与差分放大器的第二或第一输入端放大器

3. 发明申请

US20100103014A1 Multi-Level Feed-Back Digital-To-Analog Converter Using A Chopper Voltage Reference For A Switched Capacitor Sigma-Delta Analog-To-Digital Converter 有权
标题翻译：用于开关电容器Σ-Delta模数转换器的斩波电压参考的多电平反馈数模转换器
公开(公告)号：US20100103014A1
公开(公告)日：2010-04-29
申请号：US12581982
申请日：2009-10-20
申请人： Vincent Quiquempoix , Philippe Deval
发明人： Vincent Quiquempoix , Philippe Deval
IPC分类号： H03M3/00 , H03M1/66
CPC分类号： H03M3/34 , H03M3/424 , H03M3/456 , H03M3/464
摘要： A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.
摘要翻译：多位数模转换器具有产生具有偏移电压的参考电压的参考电压发生器; 用于产生多个输出电压的开关电容器级; 以及开关定序器，其控制所述开关电容器级可操作以产生用于每个输出电压的开关模式，其中每个模式具有充电阶段和转移阶段，并且其中对于至少一个输出电压，所述开关定序器提供两个开关模式，其中每个开关模式造成相反极性的偏移。

4. 发明授权

US06909388B1 Fractal sequencing schemes for offset cancellation in sampled data acquisition systems 有权
标题翻译：采样数据采集系统偏移消除的分形测序方案
公开(公告)号：US06909388B1
公开(公告)日：2005-06-21
申请号：US10874606
申请日：2004-06-23
申请人： Vincent Quiquempoix , Philippe Deval
发明人： Vincent Quiquempoix , Philippe Deval
IPC分类号： H03M3/00
CPC分类号： H03M3/356 , H03M3/43 , H03M3/438
摘要： The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.
摘要翻译：本发明涉及隔离和消除通常在采样数据模拟系统的输入端所经历的偏移电压分量。在示例性实施例中，可以在采样电路的正常操作期间执行偏移隔离和消除。在示例性实施例中，本发明将前端开关拓扑与一个或多个差分积分器级和在差分积分器级中实现的逻辑算法相结合。在操作中，电路优选地对于每个级执行多个采样，根据该算法对采样应用反转因子，并且对采样进行积分以实现偏移电压的消除而基本上不影响采样输入。

5. 发明授权

US07994958B2 Multi-level feed-back digital-to-analog converter using a chopper voltage reference for a switched capacitor sigma-delta analog-to-digital converter 有权
标题翻译：用于开关电容Σ-Δ模数转换器的斩波电压基准的多电平反馈数模转换器
公开(公告)号：US07994958B2
公开(公告)日：2011-08-09
申请号：US12581982
申请日：2009-10-20
申请人： Vincent Quiquempoix , Philippe Deval
发明人： Vincent Quiquempoix , Philippe Deval
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M3/34 , H03M3/424 , H03M3/456 , H03M3/464
摘要： A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.
摘要翻译：多位数模转换器具有产生具有偏移电压的参考电压的参考电压发生器; 用于产生多个输出电压的开关电容器级; 以及开关定序器，其控制所述开关电容器级可操作以产生用于每个输出电压的开关模式，其中每个模式具有充电阶段和转移阶段，并且其中对于至少一个输出电压，所述开关定序器提供两个开关模式，其中每个开关模式造成相反极性的偏移。

6. 发明授权

US07961126B2 Method and apparatus for dithering in multi-bit sigma-delta analog-to-digital converters 有权
标题翻译：用于在多位Σ-Δ模数转换器中抖动的方法和装置
公开(公告)号：US07961126B2
公开(公告)日：2011-06-14
申请号：US12579113
申请日：2009-10-14
申请人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
发明人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
IPC分类号： H03M1/20
CPC分类号： H03M3/33 , H03M3/424
摘要： A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
摘要翻译：多位（M位，M> 1）或多级（nlev级，nlev> 2，M位编码，M = Floor（log 2（nlev）））Σ-Δ模数转换器（ADC）具有可变分辨率多位量化器，其具有其具有随机或伪随机序列N（n）的每个电压样本的分辨率（不同输出电平的数量）和相关联的量化阈值，以提供自动动态抖动以去除不期望的 Σ-ΔADC数字输出中的空闲音调。 2和nlev之间的随机整数N（n）可以由随机或伪随机序列发生器提供，例如与数字比较器和加法器组合的Galois线性反馈移位寄存器。

7. 发明授权

US07961125B2 Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters 有权
标题翻译：用于在多位Σ-Δ数模转换器中抖动的方法和装置
公开(公告)号：US07961125B2
公开(公告)日：2011-06-14
申请号：US12571892
申请日：2009-10-01
申请人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
发明人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
IPC分类号： H03M1/20
CPC分类号： H03M3/33 , H03M3/424
摘要： A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
摘要翻译：具有可变分辨率多位量化器的多位（M位，M> 1）Σ-Delta数模转换器（DAC），其数字值输入被截断或舍入为一个分辨率随机或伪随机序列，以提供自动动态抖动，以消除Sigma-Delta DAC的模拟输出中的不需要的空闲音调。提供1和M之间的随机数N（n），并且量化器的输出处的每个M位数字值中的M-N（n）个最低有效位用数字截断器或舍入器强制为零。随机数N（n）可以由随机或伪随机序列发生器提供，例如与数字比较器和加法器结合的Galois线性反馈移位寄存器。

8. 发明申请

US20110012767A1 2-Phase Gain Calibration And Scaling Scheme For Switched Capacitor Sigma-Delta Modulator 有权
标题翻译：用于开关电容器Σ-Δ调制器的2相增益校准和缩放方案
公开(公告)号：US20110012767A1
公开(公告)日：2011-01-20
申请号：US12832599
申请日：2010-07-08
申请人： Philippe Deval , Vincent Quiquempoix
发明人： Philippe Deval , Vincent Quiquempoix
IPC分类号： H03M3/00
CPC分类号： H03M1/0663 , H03M1/0665 , H03M3/422 , H03M3/456 , H03M3/464
摘要： A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.
摘要翻译： Σ-Δ调制器可以具有多个电容器对，多个开关，用于将来自多个电容器对的任何一对电容器选择性地耦合到输入信号或参考信号，以及控制单元，用于控制通过开关以执行两阶段的电荷转移，其中可以选择任何一对电容器分配给输入信号或参考信号，并且其中在多个电荷转移之后，通过循环地旋转电容器对来执行增益误差消除，使得在旋转周期之后，每个电容器对已经被分配给输入信号的第一预定次数，并且还被分配了第二预定次数到参考信号。

9. 发明授权

US08085176B2 Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters 有权
公开(公告)号：US08085176B2
公开(公告)日：2011-12-27
申请号：US13071269
申请日：2011-03-24
申请人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
发明人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
IPC分类号： H03M1/20
CPC分类号： H03M3/33 , H03M3/424
摘要： A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

10. 发明申请

US20100103003A1 Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Analog-to-Digital Converters 有权
标题翻译：用于多位Σ-Δ模数转换器抖动的方法和装置
公开(公告)号：US20100103003A1
公开(公告)日：2010-04-29
申请号：US12579113
申请日：2009-10-14
申请人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
发明人： Philippe Deval , Vincent Quiquempoix , Alexandre Barreto
IPC分类号： H03M1/06 , H03M1/20
CPC分类号： H03M3/33 , H03M3/424
摘要： A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
摘要翻译：多位（M位，M> 1）或多级（nlev级，nlev> 2，在M位上编码，M = Floor（log2（nlev）））Σ-Δ模数转换器 ADC）具有可变分辨率多位量化器，其具有其具有随机或伪随机序列N（n）的每个电压采样的分辨率（不同输出电平的数量）和相关联的量化阈值，以提供用于去除不期望的空闲的自动动态抖动 Σ-ΔADC的数字输出中的音调。 2和nlev之间的随机整数N（n）可以由随机或伪随机序列发生器提供，例如与数字比较器和加法器组合的Galois线性反馈移位寄存器。

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