专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07920399B1 Low power content addressable memory device having selectable cascaded array segments 有权
标题翻译：具有可选择的级联阵列段的低功率内容可寻址存储器件
公开(公告)号：US07920399B1
公开(公告)日：2011-04-05
申请号：US12909701
申请日：2010-10-21
申请人： Bindiganavale S. Nataraj , Vinay Iyengar , Chetan Deshpande , Sandeep Khanna
发明人： Bindiganavale S. Nataraj , Vinay Iyengar , Chetan Deshpande , Sandeep Khanna
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.
摘要翻译：内容可寻址存储器（CAM）装置包括CAM阵列和配置电路。 CAM阵列具有多行CAM单元，每行分割成多个行段，每行段包括耦合到对应匹配线段的多个CAM单元，以及匹配线控制电路，其输入耦合到相应的匹配线段，耦合到下一行段中的匹配线段的输出，以及用于接收相应使能信号的控制终端。配置电路具有用于接收指示CAM阵列的宽度和深度配置并具有输出以产生使能信号的配置信息的输入。

2. 发明授权

US08730704B1 Content addressable memory array having local interconnects 有权
标题翻译：具有局部互连的内容可寻址存储器阵列
公开(公告)号：US08730704B1
公开(公告)日：2014-05-20
申请号：US13371236
申请日：2012-02-10
申请人： Bindiganavale S. Nataraj , John Zimmer , Sandeep Khanna , Vinay Iyengar , Chetan Deshpande
发明人： Bindiganavale S. Nataraj , John Zimmer , Sandeep Khanna , Vinay Iyengar , Chetan Deshpande
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , H01L27/1052
摘要： A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.
摘要翻译：公开了一种CAM器件，其包括CAM单元阵列，其中使用介于CAM器件的多晶硅层和CAM器件的金属层之间的导电层将CAM单元组的比较电路连接在一起。这允许CAM阵列的数据线（例如，位线和/或比较线）形成在CAM器件的金属1层中，这继而允许CAM阵列的匹配线形成在 CAM设备的金属层2层。可以是硅化物层的导电层通过从导电层穿过金属-1层延伸到金属层2的通孔连接到匹配线。

3. 发明授权

US08031501B1 Segmented content addressable memory device having pipelined compare operations 有权
标题翻译：具有流水线比较操作的分段内容可寻址存储器设备
公开(公告)号：US08031501B1
公开(公告)日：2011-10-04
申请号：US12909714
申请日：2010-10-21
申请人： Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar , Sandeep Khanna
发明人： Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar , Sandeep Khanna
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
摘要翻译：本实施例描述具有分段CAM阵列的CAM设备。 CAM阵列或单元块的每个段包括一行或多行CAM单元。基于检测到的另一个单元块的匹配条件，在搜索操作期间，CAM阵列中的一个或多个单元块被选择性地使能。通过在搜索操作期间仅在需要时选择性地使能单元块，能量消耗降低。选择性地启用单元块包括选择性地将匹配线预充电到单元块，选择性地使得字线到单元块，以及选择性地使能与单元块的比较线。根据某些实施例，CAM设备可配置为以流水线方式执行搜索操作。因此，CAM设备能够同时执行多个搜索操作。

4. 发明授权

US07920398B1 Adaptive match line charging 有权
标题翻译：自适应匹配线充电
公开(公告)号：US07920398B1
公开(公告)日：2011-04-05
申请号：US12887267
申请日：2010-09-21
申请人： Sandeep Khanna , Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar
发明人： Sandeep Khanna , Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/12
摘要： A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.
摘要翻译：一种具有任意行数的内容可寻址存储器（CAM）器件，每行包括连接到多个CAM单元的匹配线，匹配线检测器电路和预充电电路。检测器电路检测匹配线的电压，并基于检测到的匹配线电压产生反馈信号。预充电电路响应于反馈信号自适应地对匹配线进行充电。

5. 发明授权

US08787059B1 Cascaded content addressable memory array having multiple row segment activation 有权
标题翻译：具有多个行段激活的级联内容可寻址存储器阵列
公开(公告)号：US08787059B1
公开(公告)日：2014-07-22
申请号：US13311301
申请日：2011-12-05
申请人： Vinay Iyengar
发明人： Vinay Iyengar
IPC分类号： G11C15/00 , G11C15/04 , G11C7/10 , G06F17/30
CPC分类号： G11C15/04 , G06F17/30982 , G11C7/1048 , G11C15/00
摘要： A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.
摘要翻译：内容可寻址存储器（CAM）设备具有包括被划分成行段的多个CAM行的阵列，其中相应的行包括第一行段，其包括耦合到第一匹配线段的多个第一CAM单元，第二行段行段，其包括耦合到第二匹配线段的多个第二CAM单元，以及电路，用于响应于指示存储在相应行的第一行段中的数据是否为第一匹配线段的值是有选择地预充电第一匹配线段与存储在另一行的第一行段中的数据相同。在比较操作期间可以减少功耗，其中存储与相应行的第一行段相同的数据的另一行的第一行段不被启用。

6. 发明授权

US07848129B1 Dynamically partitioned CAM array 有权
标题翻译：动态分区CAM阵列
公开(公告)号：US07848129B1
公开(公告)日：2010-12-07
申请号：US12275160
申请日：2008-11-20
申请人： Chetan Deshpande , Vinay Iyengar , Bindiganavale S. Nataraj
发明人： Chetan Deshpande , Vinay Iyengar , Bindiganavale S. Nataraj
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
摘要翻译：内容可寻址存储器（CAM）装置包括比较寄存器，CAM阵列和分区逻辑。比较寄存器具有用于接收搜索关键字的输入，并且耦合到CAM阵列的输出，其包括多个可单独选择的子阵列。每个子阵列包括多个CAM单元行和一个控制电路，其中每行CAM单元耦合到匹配线，并且其中控制电路具有用于接收对应的子阵列使能信号的输入。分区逻辑具有用于接收分区选择信号的输入，并且被配置为响应于分区选择信号而生成子阵列使能信号。响应于子阵列使能信号，控制电路通过子阵列选择性地传播搜索关键字。

7. 发明授权

US07461295B1 Timing failure analysis in a semiconductor device having a pipelined architecture 有权
标题翻译：具有流水线结构的半导体器件中的定时故障分析
公开(公告)号：US07461295B1
公开(公告)日：2008-12-02
申请号：US11194067
申请日：2005-07-29
申请人： Vinay Iyengar , Bindiganavale S. Nataraj
发明人： Vinay Iyengar , Bindiganavale S. Nataraj
IPC分类号： G06F11/00
CPC分类号： G01R31/31726 , G01R31/3016
摘要： A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.
摘要翻译：一种测试具有流水线结构的半导体器件的方法。在第一流水线操作期间禁用半导体的第一流水线级的操作以在半导体器件的第二流水线级的输入处建立测试数据。执行第二流水线操作以使得第二流水线级能够使用测试数据生成中间结果。评估第二流水线操作的最终结果以确定第二流水线阶段是否产生正确的中间结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式