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1. 发明授权

US06171934B2 Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling 失效
标题翻译：通过电压循环恢复工艺损坏的铁电体中的电子特性
公开(公告)号：US06171934B2
公开(公告)日：2001-01-09
申请号：US09144297
申请日：1998-08-31
申请人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
发明人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
IPC分类号： H01L21326
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal. The voltage-cycling recovery process obviates oxygen-recovery annealing, and it allows continued use of conventional hydrogen-rich plasma processes and forming-gas anneals without the risk of permanent damage to the ferroelectric thin film.
摘要翻译：形成含有金属氧化物铁电体薄膜的集成电路。进行电压循环恢复处理以逆转由氢引起的铁电性能的降低。通过施加电压幅度为1至15伏特的104至1011个电压周期来执行电压循环恢复过程。在30-200℃范围内的较高温度下进行电压循环，提高了回收率。优选地，金属氧化物薄膜包括层状超晶格材料。优选地，层状超晶格材料包括钽酸铋钽铋或铌酸铋钽酸铋。如果集成电路制造包括成形气体退火，则在成形气体退火之后执行电压循环恢复过程。电压循环恢复过程避免氧回收退火，并且其允许继续使用常规富氢等离子体工艺和形成气体退火，而不会对铁电薄膜造成永久损坏的风险。

2. 发明授权

US06168988A Method for producing barrier-free semiconductor memory configurations 有权
标题翻译：无障碍半导体存储器配置的制造方法
公开(公告)号：US06168988A
公开(公告)日：2001-01-02
申请号：US09281691
申请日：1999-03-30
申请人： G{umlaut over (u)}nther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo
发明人： G{umlaut over (u)}nther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/10808 , H01L27/10852 , H01L27/11517 , H01L28/55
摘要： A method for producing an integrated semiconductor memory configuration, in particular uses ferroelectric materials as storage dielectrics. A conductive connection between a first electrode of a storage capacitor and a selection transistor is produced only after deposition of the storage dielectric.
摘要翻译：一种用于制造集成半导体存储器配置的方法，特别地使用铁电材料作为存储电介质。存储电容器的第一电极和选择晶体管之间的导电连接仅在沉积存储电介质之后产生。

3. 发明授权

US06322849B2 Recovery of electronic properties in hydrogen-damaged ferroelectrics by low-temperature annealing in an inert gas 失效
标题翻译：在惰性气体中通过低温退火在氢损坏的铁电体中回收电子性能
公开(公告)号：US06322849B2
公开(公告)日：2001-11-27
申请号：US09191634
申请日：1998-11-13
申请人： Vikram Joshi , Narayan Solayappan , Walter Hartner , Günther Schindler
发明人： Vikram Joshi , Narayan Solayappan , Walter Hartner , Günther Schindler
IPC分类号： B05D512
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An inert-gas recovery anneal is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The inert-gas recovery anneal is conducted in an unreactive gas atmosphere at a temperature range from 300° to 1000° C. for a time period from one minute to two hours. Preferably, the metal-oxide thin film comprises layered superlattice material. Preferably, the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the inert-gas recovery anneal is performed after the forming-gas anneal, preferably at or near the same temperature and for the same time duration as the forming-gas anneal. The inert-gas recovery anneal obviates oxygen-recovery annealing, and it allows continued use of conventional hydrogen-rich plasma processes and forming-gas anneals without the risk of permanent damage to the ferroelectric thin film. The unreactive gas atmosphere can contain a pure unreactive gas or a mixture of unreactive gases. The unreactive gas can be any relatively unreactive gas, such as nitrogen or argon.
摘要翻译：形成含有金属氧化物铁电体薄膜的集成电路。进行惰性气体回收退火以逆转由氢引起的铁电性能的降低。惰性气体回收退火在300〜1000℃的无反应气体气氛中进行1分钟〜2小时。优选地，金属氧化物薄膜包括层状超晶格材料。优选地，层状超晶格材料包括铋铋钽酸锶或铌酸铋钽酸铋。如果集成电路制造包括成形气体退火，则惰性气体回收退火在成形气体退火之后进行，优选在与成形气体退火相同或接近相同的温度和相同的持续时间。惰性气体回收退火避免了氧回收退火，并且允许继续使用常规富氢等离子体工艺和形成气体退火，而不会对铁电薄膜造成永久性损坏的风险。非活性气体气氛可以含有纯的非反应性气体或非反应性气体的混合物。非反应性气体可以是任何相对不反应的气体，例如氮气或氩气。

4. 发明授权

US5962069A Process for fabricating layered superlattice materials and AB0.sub.3 type metal oxides without exposure to oxygen at high temperatures 失效
标题翻译：用于在高温下不暴露于氧气的层压超晶格材料和AB03型金属氧化物的制造方法
公开(公告)号：US5962069A
公开(公告)日：1999-10-05
申请号：US900270
申请日：1997-07-25
申请人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
发明人： Gunther Schindler , Walter Hartner , Carlos Mazure , Narayan Solayappan , Vikram Joshi , Gary F. Derbenwick
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , B05D3/02 , H01L21/3205
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1275 , C23C18/1283 , C23C18/1295
摘要： A liquid precursor containing a metal is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 260.degree. C., RTP baked at a temperature of 300.degree. C. in oxygen, RTP baked at a temperature of 650.degree. C. in nitrogen, and annealed at a temperature of 800.degree. C. in nitrogen to form a strontium bismuth tantalate layered superlattice material. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. Alternatively, the second anneal may be performed in oxygen at a temperature of 600.degree. C. or less. In this manner, a high electronic quality thin film of a layered superlattice material is fabricated without a high-temperature oxygen anneal.
摘要翻译：将含有金属的液体前体施加到第一电极上，在空气中在160℃的第一温度下干燥，然后在260℃的第二温度下干燥，在氧气中在300℃下进行RTP烘焙，RTP 在氮气中在650℃下烘烤，并在氮气中在800℃的温度下退火，形成钽酸铋锶层状超晶格材料。沉积第二电极，然后将器件图案化以形成电容器，并且在氮气中在800℃的温度下进行第二次退火。或者，第二退火可以在600℃以下的温度下进行。以这种方式，在没有高温氧退火的情况下制造层状超晶格材料的高电子质量薄膜。

5. 发明申请

US20140035154A1 CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE 有权
标题翻译：芯片包装和制造芯片包装的方法
公开(公告)号：US20140035154A1
公开(公告)日：2014-02-06
申请号：US13564922
申请日：2012-08-02
申请人： Ottmar Geitner , Walter Hartner , Maciej Wojnowski , Ulrich Wachter , Michael Bauer , Andreas Stueckjuergen
发明人： Ottmar Geitner , Walter Hartner , Maciej Wojnowski , Ulrich Wachter , Michael Bauer , Andreas Stueckjuergen
IPC分类号： H01L23/31 , H01L21/56
CPC分类号： H01L24/96 , H01L23/3128 , H01L23/49855 , H01L23/5389 , H01L23/66 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/2105 , H01L2224/211 , H01L2224/214 , H01L2224/24051 , H01L2224/32245 , H01L2224/73151 , H01L2224/73259 , H01L2224/73267 , H01L2924/12032 , H01L2924/12042 , H01L2924/1301 , H01L2924/13034 , H01L2924/1304 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/142 , H01L2924/15311 , H01L2924/18162 , H01L2924/014 , H01L2924/01029 , H01L2924/01013 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01046 , H01L2924/0103 , H01L2924/01028 , H01L2924/01026 , H01L2224/13 , H01L2224/21 , H01L2924/00 , H01L2924/00014
摘要： A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
摘要翻译：提供了芯片封装，芯片封装包括：芯片，包括形成在芯片正面上的至少一个接触焊盘; 至少部分地围绕所述芯片并且覆盖所述至少一个接触垫的封装材料; 以及通过所述封装材料形成的至少一个电互连，其中所述至少一个电互连构造成将所述至少一个接触焊盘从所述芯片前侧的芯片封装第一侧电重定向到形成在所述芯片前侧上的至少一个焊料结构芯片封装第二面在芯片背面。

6. 发明授权

US07468307B2 Semiconductor structure and method 有权
标题翻译：半导体结构与方法
公开(公告)号：US07468307B2
公开(公告)日：2008-12-23
申请号：US11476497
申请日：2006-06-28
申请人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L21/76
CPC分类号： H01L21/743 , H01L23/535 , H01L29/0653 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.
摘要翻译：半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。可以在隔离沟槽内形成与半导体衬底的接触。

7. 发明申请

US20070018195A1 Semiconductor structure and method 有权
标题翻译：半导体结构与方法
公开(公告)号：US20070018195A1
公开(公告)日：2007-01-25
申请号：US11476497
申请日：2006-06-28
申请人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L29/74
CPC分类号： H01L21/743 , H01L23/535 , H01L29/0653 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.
摘要翻译：半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。可以在隔离沟槽内形成与半导体衬底的接触。

8. 发明授权

US06586348B2 Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation anneal but while still amorphous and then thermally annealing to crystallize 有权
标题翻译：通过在成核退火之后对膜进行图案化但是仍然是无定形然后热退火以结晶的方法来防止蚀刻对金属氧化物膜的损伤
公开(公告)号：US06586348B2
公开(公告)日：2003-07-01
申请号：US09850585
申请日：2001-05-07
申请人： Walter Hartner , Günther Schindler , Frank Hintermaier , Volker Weinrich
发明人： Walter Hartner , Günther Schindler , Frank Hintermaier , Volker Weinrich
IPC分类号： H01L2131
CPC分类号： H01L21/02197 , H01L21/02356 , H01L21/31122 , H01L21/31691 , H01L21/32136 , H01L28/55
摘要： After an SBT layer is precipitated onto a substrate, the SBT layer is structured as a still amorphous layer. Only subsequently is it subjected to a crystallization process. Layers produced in this manner have a relatively high degree of dielectric strength and have no stoichiometric deviations on the etched edges.
摘要翻译：在SBT层沉积到衬底上之后，SBT层被构造为静止非晶层。只有随后才进行结晶过程。以这种方式生产的层具有相对高的介电强度，并且在蚀刻的边缘上不具有化学计量偏差。

9. 发明申请

US20110256688A1 SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT 有权
公开(公告)号：US20110256688A1
公开(公告)日：2011-10-20
申请号：US13156970
申请日：2011-06-09
申请人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L21/76
CPC分类号： H01L21/76802 , H01L21/76286 , H01L21/76877 , H01L21/84 , H01L27/1203
摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

10. 发明授权

US07351642B2 Deglaze route to compensate for film non-uniformities after STI oxide processing 失效
标题翻译： DeGaaze路径补偿STI氧化物处理后的膜不均匀性
公开(公告)号：US07351642B2
公开(公告)日：2008-04-01
申请号：US11036536
申请日：2005-01-14
申请人： Walter Hartner , Joseph Page , Jonathan Davis
发明人： Walter Hartner , Joseph Page , Jonathan Davis
IPC分类号： H01L21/76
CPC分类号： H01L21/31055
摘要： A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.
摘要翻译：一种用于补偿晶片上的径向不均匀性的方法和方法，包括以下步骤：在CMP工艺之后使膜周围的旋转基座的轴线上的膜的旋转厚度不均匀性居中; 将喷嘴定位在旋转处理单元中以沿着晶片的半径引导蚀刻溶液; 从喷嘴调节蚀刻溶液的流动; 调整旋转基座的旋转速度以控制蚀刻溶液的停留时间; 并协调旋转基座的旋转速度，蚀刻溶液的流动和喷嘴的定位，以最大限度地去除材料。该方法可用于补偿STI氧化物的碗形不均匀性。这些非均匀性在CMP过程之后得到补偿和解决。

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