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1. 发明授权

US5942952A VCO with multiple negative differential resistance devices 失效
标题翻译： VCO具有多个负差分电阻器件
公开(公告)号：US5942952A
公开(公告)日：1999-08-24
申请号：US903081
申请日：1997-07-30
申请人： Vijay K. Nair , Nada El-Zein , Kumar Shiralagi , George N. Maracas , Herbert Goronkin
发明人： Vijay K. Nair , Nada El-Zein , Kumar Shiralagi , George N. Maracas , Herbert Goronkin
IPC分类号： H01L27/06 , H01L29/88 , H03B1/00 , H03B7/06 , H03B7/14
CPC分类号： H03B7/06 , H01L27/0605 , H01L29/882 , H03B2200/0062 , H03B2201/02 , H03B7/143
摘要： A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.
摘要翻译： VCO包括具有与晶体管的源极端子串联耦合的多个负差分电阻器件的晶体管，其中每个器件具有负的差分电阻工作区域。偏置电路耦合到漏极和栅极端子以及操作电压，其工作电压将振荡器设置为在负差分电阻器件中的至少一个的负差分电阻区域中工作，使得在输出端子处产生选定频率的振荡。连接晶体管，多个N器件，DC偏置电路和工作电压，使得振荡器负差分电阻工作区域分别大于每个器件负差分工作区域的N倍。

2. 发明授权

US06452205B2 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06452205B2
公开(公告)日：2002-09-17
申请号：US09819438
申请日：2001-03-29
申请人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
发明人： Raymond K. Tsui , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L29/045 , H01L29/127
摘要： A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.
摘要翻译：一种稀疏载体器件，包括由第一材料形成并具有宽度（w）和长度的晶体结构（26）和由第二材料形成并且至少位于第二材料的量子点（30）的晶体结构（10）在晶面上有一排（26）。至少一行量子点（30）沿着结晶小面（26）的长度延伸，并且是至少一个量子点（30）宽（w）和多个量子点长。由晶面（26）的宽度（w）确定的量子点行数。量子点行（30）形成基于稀疏或单电子器件的电路的构建块。

3. 发明授权

US5943574A Method of fabricating 3D multilayer semiconductor circuits 失效
标题翻译：制造3D多层半导体电路的方法
公开(公告)号：US5943574A
公开(公告)日：1999-08-24
申请号：US27915
申请日：1998-02-23
申请人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
发明人： Saied N. Tehrani , Kumar Shiralagi , Herbert Goronkin
IPC分类号： H01L21/336 , H01L21/768 , H01L27/06 , H01L27/092 , H01L29/786
CPC分类号： H01L29/6675 , H01L21/76838 , H01L27/0688 , H01L27/0922 , H01L29/78642
摘要： A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
摘要翻译：一种制造3D半导体电路的方法，包括向其上形成有导电层的掺杂多晶硅进行图案化和退火，以形成半导体器件的第一单晶多晶硅端子。绝缘栅极触点与端子垂直间隔开，以便限定垂直通孔，并且多孔沉积在通孔中以形成传导通道。通孔中的多晶硅的上部被掺杂以形成用于半导体器件的第二端子，并且将多晶硅退火以将其转换成单晶粒多晶硅。在第二端子上沉积和图案化第二导电层以限定半导体器件的第二端子触点。

4. 发明授权

US5591666A Semiconductor device and method of fabrication 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5591666A
公开(公告)日：1997-01-07
申请号：US511776
申请日：1995-08-07
申请人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond K. Tsui , Herbert Goronkin
IPC分类号： H01L21/205 , H01L21/20 , H01L29/88
CPC分类号： H01L21/02395 , H01L21/02546 , H01L21/0262 , H01L21/02639 , Y10S117/902 , Y10S117/913 , Y10S438/973
摘要： A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.
摘要翻译：一种制造半导体器件的方法，包括限定衬底的表面上的区域，在该区域上选择性地生长具有至少一个限定的结晶小面的晶体材料，以及在晶面上选择性地生长半导体器件。在第二实施例中，在衬底的表面上限定一个区域，并且使用化学束外延在该区域上选择性地在至少一个限定的晶面上生长砷化铟层。

5. 发明授权

US06211530B1 Sparse-carrier devices and method of fabrication 失效
标题翻译：稀疏载波器件及其制造方法
公开(公告)号：US06211530B1
公开(公告)日：2001-04-03
申请号：US09097026
申请日：1998-06-12
申请人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
发明人： Herbert Goronkin , Raymond K. Tsui , Ruth Y. Zhang , Kumar Shiralagi
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , H01L21/02395 , H01L21/02463 , H01L21/02494 , H01L21/02546 , H01L21/02601 , H01L21/0262 , H01L21/02642 , H01L29/045 , H01L29/127 , H01L29/7613
摘要： A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.
摘要翻译：稀疏载体器件包括晶体结构，其晶体结构在相对端具有接触。量子点形成在小平面上的第一和第二行中，大约一个量子点宽，并且多个量子点长，第一行中的量子点彼此间隔开小于量子点之间的第二距离的第一距离在第二行中的第一行和相邻的量子点。第一距离足够小以允许相邻量子点之间的载流子隧穿，并且第二距离足够大以基本上防止相邻量子点之间的隧道，并且足够小以允许相邻量子点之间的库仑相互作用。电触点形成在行的相对端处，以允许载流子在第一行和第二行中将量子点隧穿。

6. 发明授权

US5756154A Masking methods during semiconductor device fabrication 失效
标题翻译：半导体器件制造期间的掩模方法
公开(公告)号：US5756154A
公开(公告)日：1998-05-26
申请号：US583329
申请日：1996-01-05
申请人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
发明人： Kumar Shiralagi , Raymond Tsui , Herbert Goronkin
IPC分类号： H01L21/316 , H01L21/20 , B05D1/32 , B05D3/00 , C08J7/18
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a substrate, and in a preferred embodiment a silicon substrate. The surface is hydrogen terminated (or hydrogenated) and a metal mask is positioned on the surface so as to define a growth area and an unmasked portion on the surface. Ozone is generated at the surface, at least in the unmasked area, by exposing the surface to a light having a wavelength approximately 185 nm (an oxygen absorbing peak), so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating.
摘要翻译：公开了一种在制造半导体器件期间掩蔽表面的方法，其包括提供衬底，并且在优选实施例中为硅衬底。表面是氢封端（或氢化），并且金属掩模位于表面上，以便在表面上限定生长区域和未掩模部分。通过将表面暴露于波长约185nm的光（氧吸收峰），至少在未掩模的区域中，在表面产生臭氧，以便在表面的未掩模部分上生长氧化膜。除去金属掩模，然后氧化膜用作进一步操作的掩模，并且可以通过加热容易地原位除去。

7. 发明授权

US5846609A Masking methods for semiconductor materials 失效
标题翻译：半导体材料的掩模方法
公开(公告)号：US5846609A
公开(公告)日：1998-12-08
申请号：US775934
申请日：1997-01-03
申请人： Kumar Shiralagi
发明人： Kumar Shiralagi
IPC分类号： H01L21/205 , H01L21/033 , H01L21/20 , H01L21/208 , C08J7/04
CPC分类号： H01L21/0332 , H01L21/0237 , H01L21/02389 , H01L21/02395 , H01L21/0242 , H01L21/02529 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/0334
摘要： A method of forming a mask including providing a fluid from a group including oxygen based, nitrogen based, or carbon based fluids, introducing a substrate of semiconductor material into the fluid, and growing a film with thickness in a range of 10-20 .ANG. on a surface by converting the fluid adjacent the surface into a reactive species. The reactive species is created by directing light having a wavelength at the absorption peak of the fluid so as to convert the fluid into the reactive species. The surface of the substrate reacts with the reactive species to form the film.
摘要翻译：一种形成掩模的方法，包括从包括氧基，氮基或碳基流体的组中提供流体，将半导体材料的基底引入流体中，并且将厚度范围为10-20的膜生长通过将邻近表面的流体转化为反应性物质来实现表面。通过将具有在流体的吸收峰处的波长的光引导以将流体转化为反应性物质来产生反应性物质。衬底的表面与反应性物质反应形成膜。

8. 发明授权

US06172420B2 Silicon delta-doped gallium arsenide/indium arsenide heterojunction OHMIC contact 失效
标题翻译：硅三角掺杂砷化镓/砷化铟异质结OHMIC接触
公开(公告)号：US06172420B2
公开(公告)日：2001-01-09
申请号：US09502702
申请日：2000-02-11
申请人： Kumar Shiralagi
发明人： Kumar Shiralagi
IPC分类号： H01L2348
CPC分类号： H01L21/28575 , H01L29/205 , Y10S438/933 , Y10S438/934 , Y10S438/938
摘要： An ohmic contact including a gallium arsenide substrate having an epitaxially grown crystalline layer of indium arsenide on the substrate. The crystalline material and the substrate define an interface, layers are n-doped with silicon close to the interface.
摘要翻译：包括在衬底上具有外延生长的砷化铟晶体层的砷化镓衬底的欧姆接触。结晶材料和衬底限定了界面，层在接近界面处用硅掺杂硅。

9. 发明授权

US6124146A Resistless device fabrication method 失效
标题翻译：无电阻器件制造方法
公开(公告)号：US6124146A
公开(公告)日：2000-09-26
申请号：US79634
申请日：1998-05-15
申请人： Kumar Shiralagi
发明人： Kumar Shiralagi
IPC分类号： H01L21/285 , H01L21/00
CPC分类号： H01L21/2855
摘要： A method of depositing a material to a semiconductor device having a first mesa structure, a second mesa structure and a valley. Material is deposited from a first angular direction sufficient to substantially mask the valley with a first of the mesa structures and from a second angular direction sufficient to substantially mask the valley with the second mesa structure to form a first lip and a second lip on the respective first and second mesa structures overlying the valley and defining a space therebetween less than the width of the valley. Material is then deposited to the device from a third direction in substantial opposition to the device, the space operating to guide material deposition to the valley to provide discrete material deposition in the valley to form a discrete feature in the valley.
摘要翻译：一种将材料沉积到具有第一台面结构，第二台面结构和谷的半导体器件的方法。材料从第一角度方向沉积，该第一角度方向足以基本上用第一台面结构掩蔽谷，并且从第二角度方向沉积足以基本上利用第二台面结构掩蔽谷以形成第一唇缘和第二唇缘第一和第二台面结构覆盖在谷上并且在其之间限定小于谷宽度的空间。然后将材料从与第三方向相反的装置沉积到装置上，该装置的作用是将材料沉积到谷上以在谷中提供离散的材料沉积，以在谷中形成离散的特征。

10. 发明授权

US5904552A Method of resistless patterning of a substrate for implantation 失效
标题翻译：用于植入的基底的无阻抗图案化方法
公开(公告)号：US5904552A
公开(公告)日：1999-05-18
申请号：US806270
申请日：1997-02-25
申请人： Kumar Shiralagi , Danny L. Thompson
发明人： Kumar Shiralagi , Danny L. Thompson
IPC分类号： H01L21/033 , H01L21/265 , H01L21/266 , H01L21/425
CPC分类号： H01L21/2652 , H01L21/0332 , H01L21/266
摘要： A method of ion implanting a substrate is disclosed, which includes providing a substrate having a surface. A sacrificial layer of semiconductor material is formed on the surface and resistlessly patterning to define masked and unmasked portions. The unmasked portions are etched away to form an implantation mask on the substrate. Ions are implanted in the substrate underlying the etched away unmasked portions and the sacrificial layer is removed.
摘要翻译：公开了一种离子注入衬底的方法，其包括提供具有表面的衬底。半导体材料的牺牲层形成在表面上，并且无阻地构图以限定掩模和未掩模部分。将未掩模的部分蚀刻掉以在衬底上形成注入掩模。将离子植入到蚀刻掉的未掩模部分下方的衬底中，并且去除牺牲层。

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