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1. 发明申请

US20070002827A1 Automated serial protocol target port transport layer retry mechanism 审中-公开
标题翻译：自动串行协议目标端口传输层重试机制
公开(公告)号：US20070002827A1
公开(公告)日：2007-01-04
申请号：US11171985
申请日：2005-06-30
申请人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , Kiran Vemula , William Halleck , Ankit Parikh
发明人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , Kiran Vemula , William Halleck , Ankit Parikh
IPC分类号： H04L12/28
CPC分类号： G06F13/385 , H04L1/1607 , H04L49/90
摘要： Disclosed is a target port that implements a transport layer retry (TLR) mechanism. The target port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.
摘要翻译：公开了实现传输层重试（TLR）机制的目标端口。目标端口包括具有发射传输层和接收传输层的电路，其中发射和接收传输层都耦合到链路。发送传输层的发送协议处理器控制串行协议中的TLR机制。接收传输层的接收协议处理器耦合到发射传输层，同样控制序列化协议中的TLR机制。

2. 发明申请

US20070011333A1 Automated serial protocol initiator port transport layer retry mechanism 审中-公开
标题翻译：自动串行协议发起端口传输层重试机制
公开(公告)号：US20070011333A1
公开(公告)日：2007-01-11
申请号：US11172318
申请日：2005-06-30
申请人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , Kiran Vemula , William Halleck , Ankit Parikh
发明人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , Kiran Vemula , William Halleck , Ankit Parikh
IPC分类号： G06F15/16
CPC分类号： H04L69/28 , H04L69/326
摘要： Disclosed is an initiator port that implements a transport layer retry (TLR) mechanism. The initiator port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.
摘要翻译：公开了实现传输层重试（TLR）机制的发起者端口。发起端口包括具有发射传输层和接收传输层的电路，其中发射和接收传输层都耦合到链路。发送传输层的发送协议处理器控制串行协议中的TLR机制。接收传输层的接收协议处理器耦合到发射传输层，同样控制序列化协议中的TLR机制。

3. 发明授权

US07415549B2 DMA completion processing mechanism 有权
标题翻译： DMA完成处理机制
公开(公告)号：US07415549B2
公开(公告)日：2008-08-19
申请号：US11237455
申请日：2005-09-27
申请人： Kiran Vemula , Victor Lau , Pak-lung Seto , Nai-Chih Chang , William Halleck , Suresh Chemudupati , Ankit Parikh , Gary Y. Tsao
发明人： Kiran Vemula , Victor Lau , Pak-lung Seto , Nai-Chih Chang , William Halleck , Suresh Chemudupati , Ankit Parikh , Gary Y. Tsao
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
摘要翻译：根据一个实施例，公开了一种存储装置。存储设备包括具有一个或多个通道的端口和直接存储器访问（DMA）描述符管理器（DM）。 DM生成并跟踪描述符的完成。 DM包括用于跟踪在第一通道处接收的输入/输出（I / O）上下文的一个或多个字段的第一完成查找表。

4. 发明申请

US20070073921A1 DMA completion processing mechanism 有权
标题翻译： DMA完成处理机制
公开(公告)号：US20070073921A1
公开(公告)日：2007-03-29
申请号：US11237455
申请日：2005-09-27
申请人： Kiran Vemula , Victor Lau , Pak-lung Seto , Nai-Chih Chang , William Halleck , Suresh Chemudupati
发明人： Kiran Vemula , Victor Lau , Pak-lung Seto , Nai-Chih Chang , William Halleck , Suresh Chemudupati
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
摘要翻译：根据一个实施例，公开了一种存储装置。存储设备包括具有一个或多个通道的端口和直接存储器访问（DMA）描述符管理器（DM）。 DM生成并跟踪描述符的完成。 DM包括用于跟踪在第一通道处接收的输入/输出（I / O）上下文的一个或多个字段的第一完成查找表。

5. 发明授权

US07506080B2 Parallel processing of frame based data transfers 失效
标题翻译：基于帧的数据传输的并行处理
公开(公告)号：US07506080B2
公开(公告)日：2009-03-17
申请号：US11229100
申请日：2005-09-16
申请人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , William Halleck
发明人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , William Halleck
IPC分类号： G06F13/28 , G06F13/00 , H04L12/28 , H04L12/56
CPC分类号： H04L49/901 , G06F13/28 , H04L49/90
摘要： A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.
摘要翻译：基于帧的数据传送设备包括接收帧解析器，接收帧处理器和DMA引擎。接收帧解析器接收帧，从帧中的成帧信息存储在接收头队列中，并将来自帧的信息单元存储在信息单元缓冲器中。接收帧处理器耦合到接收头部队列。接收帧处理器读取由成帧信息中的标签字段确定的传输层任务上下文，确定如何处理来自传输层任务上下文和成帧信息的帧，生成DMA描述符，并存储更新的传输层任务上下文。 DMA引擎耦合到信息单元缓冲器和接收帧处理器。 DMA引擎读取DMA任务上下文，通过处理DMA描述符将信息单元传送到目的地存储器，并存储更新的DMA任务上下文。

6. 发明申请

US20070067504A1 Parallel processing of frame based data transfers 失效
标题翻译：基于帧的数据传输的并行处理
公开(公告)号：US20070067504A1
公开(公告)日：2007-03-22
申请号：US11229100
申请日：2005-09-16
申请人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , William Halleck
发明人： Victor Lau , Pak-lung Seto , Suresh Chemudupati , Naichih Chang , William Halleck
IPC分类号： G06F13/28
CPC分类号： H04L49/901 , G06F13/28 , H04L49/90
摘要： A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.
摘要翻译：基于帧的数据传送设备包括接收帧解析器，接收帧处理器和DMA引擎。接收帧解析器接收帧，从帧中的成帧信息存储在接收头队列中，并将来自帧的信息单元存储在信息单元缓冲器中。接收帧处理器耦合到接收头部队列。接收帧处理器读取由成帧信息中的标签字段确定的传输层任务上下文，确定如何处理来自传输层任务上下文和成帧信息的帧，生成DMA描述符，并存储更新的传输层任务上下文。 DMA引擎耦合到信息单元缓冲器和接收帧处理器。 DMA引擎读取DMA任务上下文，通过处理DMA描述符将信息单元传送到目的地存储器，并存储更新的DMA任务上下文。

7. 发明申请

US20070073955A1 Multi-function PCI device 审中-公开
标题翻译：多功能PCI设备
公开(公告)号：US20070073955A1
公开(公告)日：2007-03-29
申请号：US11239741
申请日：2005-09-29
申请人： Joseph Murray , Sailesh Bissessur , Shailendra Jha , Victor Lau , Bruno DiPlacido , Nai-Chih Chang , Suresh Chemudupati
发明人： Joseph Murray , Sailesh Bissessur , Shailendra Jha , Victor Lau , Bruno DiPlacido , Nai-Chih Chang , Suresh Chemudupati
IPC分类号： G06F13/36
CPC分类号： G06F13/385
摘要： A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.
摘要翻译：公开了一种多功能外围组件互连（PCI）设备。该设备包括与第一PCI功能相关联的第一配置数据结构，与第二PCI功能相关联的第二配置数据结构和PCI桥，其耦合第一和第二配置数据结构。 PCI桥接器代表第一和第二功能处理事务。

8. 发明申请

US20070011548A1 Centralized error signaling and logging 有权
标题翻译：集中错误信号和记录
公开(公告)号：US20070011548A1
公开(公告)日：2007-01-11
申请号：US11165725
申请日：2005-06-24
申请人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
发明人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
IPC分类号： H04L1/00 , G06F11/00 , H03M13/00 , G08C25/00 , G06F11/30
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0781
摘要： A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括一个或多个错误接收单元，每个错误接收单元可操作以从协议中的给定层接收错误请求，并将接收到的错误请求同步到所有层的公共时钟域，并且仲裁器单元可操作以接收来自一个或多个错误接收单元的同步错误请求，将错误请求编码到公共错误互连上，并将编码的错误请求跨越互连路由到配置空间。

9. 发明授权

US07480832B2 Centralized error signaling and logging 有权
标题翻译：集中错误信号和记录
公开(公告)号：US07480832B2
公开(公告)日：2009-01-20
申请号：US11165725
申请日：2005-06-24
申请人： Suresh Chemudupati , Victor T. Lau , Bruno DiPlacido , Eric J. DeHaemer
发明人： Suresh Chemudupati , Victor T. Lau , Bruno DiPlacido , Eric J. DeHaemer
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0781
摘要： A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括一个或多个错误接收单元，每个错误接收单元可操作以从协议中的给定层接收错误请求，并将接收到的错误请求同步到所有层的公共时钟域，并且仲裁器单元可操作以接收来自一个或多个错误接收单元的同步错误请求，将错误请求编码到公共错误互连上，并将编码的错误请求跨越互连路由到配置空间。

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