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1. 发明申请

US20070011548A1 Centralized error signaling and logging 有权
标题翻译：集中错误信号和记录
公开(公告)号：US20070011548A1
公开(公告)日：2007-01-11
申请号：US11165725
申请日：2005-06-24
申请人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
发明人： Suresh Chemudupati , Victor Lau , Bruno DiPlacido , Eric DeHaemer
IPC分类号： H04L1/00 , G06F11/00 , H03M13/00 , G08C25/00 , G06F11/30
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0781
摘要： A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括一个或多个错误接收单元，每个错误接收单元可操作以从协议中的给定层接收错误请求，并将接收到的错误请求同步到所有层的公共时钟域，并且仲裁器单元可操作以接收来自一个或多个错误接收单元的同步错误请求，将错误请求编码到公共错误互连上，并将编码的错误请求跨越互连路由到配置空间。

2. 发明申请

US20070073955A1 Multi-function PCI device 审中-公开
标题翻译：多功能PCI设备
公开(公告)号：US20070073955A1
公开(公告)日：2007-03-29
申请号：US11239741
申请日：2005-09-29
申请人： Joseph Murray , Sailesh Bissessur , Shailendra Jha , Victor Lau , Bruno DiPlacido , Nai-Chih Chang , Suresh Chemudupati
发明人： Joseph Murray , Sailesh Bissessur , Shailendra Jha , Victor Lau , Bruno DiPlacido , Nai-Chih Chang , Suresh Chemudupati
IPC分类号： G06F13/36
CPC分类号： G06F13/385
摘要： A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.
摘要翻译：公开了一种多功能外围组件互连（PCI）设备。该设备包括与第一PCI功能相关联的第一配置数据结构，与第二PCI功能相关联的第二配置数据结构和PCI桥，其耦合第一和第二配置数据结构。 PCI桥接器代表第一和第二功能处理事务。

3. 发明申请

US20060271718A1 Method of preventing error propagation in a PCI / PCI-X / PCI express link 审中-公开
标题翻译：防止PCI / PCI-X / PCI快速链路中的错误传播的方法
公开(公告)号：US20060271718A1
公开(公告)日：2006-11-30
申请号：US11139222
申请日：2005-05-27
申请人： Bruno DiPlacido , Joseph Murray , Victor Lau , Marc Goldschmidt , Eric DeHaemer
发明人： Bruno DiPlacido , Joseph Murray , Victor Lau , Marc Goldschmidt , Eric DeHaemer
IPC分类号： G06F13/24
CPC分类号： G06F11/0745 , G06F11/0766 , G06F11/0793
摘要： An embodiment is a method and apparatus to prevent the propagation of an error in a transmission from an I/O processor of a peripheral device to a host in a computer system utilizing a PCI, PCI-X, or PCI Express link. An embodiment detects an error in a transmission, may shut down the transmission path, and further intercepts the confirmation message before the confirmation message can be sent to the host
摘要翻译：一个实施例是一种防止传输中的错误从外设设备的I / O处理器传播到使用PCI，PCI-X或PCI Express链路的计算机系统中的主机的方法和装置。实施例检测到传输中的错误，可以关闭传输路径，并且在确认消息可以被发送到主机之前进一步拦截确认消息

4. 发明授权

US07480832B2 Centralized error signaling and logging 有权
标题翻译：集中错误信号和记录
公开(公告)号：US07480832B2
公开(公告)日：2009-01-20
申请号：US11165725
申请日：2005-06-24
申请人： Suresh Chemudupati , Victor T. Lau , Bruno DiPlacido , Eric J. DeHaemer
发明人： Suresh Chemudupati , Victor T. Lau , Bruno DiPlacido , Eric J. DeHaemer
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0781
摘要： A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit operable to receive the synchronized error requests from the one or more error receiving units, encode the error requests onto on a common error interconnect, and route the encoded error requests across the interconnect to configuration space.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，设备包括一个或多个错误接收单元，每个错误接收单元可操作以从协议中的给定层接收错误请求，并将接收到的错误请求同步到所有层的公共时钟域，并且仲裁器单元可操作以接收来自一个或多个错误接收单元的同步错误请求，将错误请求编码到公共错误互连上，并将编码的错误请求跨越互连路由到配置空间。

5. 发明授权

US06226292B1 Frame replication in a network switch for multi-port frame forwarding 失效
标题翻译：用于多端口帧转发的网络交换机中的帧复制
公开(公告)号：US06226292B1
公开(公告)日：2001-05-01
申请号：US09044285
申请日：1998-03-19
申请人： Bruno DiPlacido
发明人： Bruno DiPlacido
IPC分类号： H04L1228
CPC分类号： H04L47/15 , H04L49/201 , H04L49/352 , H04L49/90 , H04L49/901
摘要： A network data switch includes a transmit buffer memory containing transmit buffers allocated to temporarily store data frames being transmitted on attached network links. Multicast frames are replicated into different transmit buffers as necessary for transmission on the corresponding network links. Multiple-cycle write and read phases of the transmit buffer memory are defined, and the transmit buffer memory is operated in different modes for unicast and multicast operation. For a unicast frame, multi-word segments of the frame are written into the correct transmit buffer during successive write phases. Each segment is written during a write phase as a burst of data words at a high data rate. For a multicast frame, words of the frame are written in a time-slice manner into the transmit buffers for the network links on which the frame is to be transmitted. The words are written during successive write phases. During each write phase a single word is written to all the necessary transmit buffers by being supplied to the buffer memory data input while the buffers are sequentially addressed.
摘要翻译：网络数据交换机包括发送缓冲存储器，其包含分配用于临时存储在附接网络链路上发送的数据帧的发送缓冲器。将组播帧复制到不同的发送缓冲器中，以便在相应的网络链路上进行传输。定义了发送缓冲存储器的多周期写入和读取阶段，发送缓冲存储器以不同的模式进行单播和多播操作。对于单播帧，在连续写入阶段期间，帧的多字段被写入正确的发送缓冲器。每个段在写入阶段被写入高数据速率的数据字串。对于多播帧，将帧的字以时间片的方式写入用于要在其上发送帧的网络链路的发送缓冲器中。这些单词在连续写入阶段写入。在每个写入阶段期间，当缓冲器被顺序寻址时，通过提供给缓冲存储器数据输入将单个字写入所有必要的发送缓冲器。

6. 发明授权

US6092108A Dynamic threshold packet filtering of application processor frames 失效
标题翻译：应用处理器帧的动态阈值包过滤
公开(公告)号：US6092108A
公开(公告)日：2000-07-18
申请号：US44804
申请日：1998-03-19
申请人： Bruno DiPlacido , Lawrence A. Boxer
发明人： Bruno DiPlacido , Lawrence A. Boxer
IPC分类号： G06F13/40 , G06F13/38 , G06F15/17
CPC分类号： G06F13/4022
摘要： A multiported device is provided connected to a switching device providing switching functions. The multiported device receives frames and is connected to an application processor. Some of the received frames are passed to the application processor via an application processor port having a port bandwidth. The multiported device includes an application receive buffer having a receive buffer size for storing frames and providing frames to the application processor for processing. A programmable logic unit is provided for monitoring a level of data in the receive buffer and monitoring a type of frame forwarded to said application processor. The frames each have a discriptor frame associated with it with data indicating one or more of priority status and broadcast/unicast status. The logic unit monitors the level of data based on at least one threshold level for dropping frames upon a data level in said receive buffer reaching the threshold level which have a status. The status is one the one or more of priority status and broadcast/unicast status.
摘要翻译：提供连接到提供切换功能的开关装置的多端口装置。多端口设备接收帧并连接到应用处理器。一些接收到的帧经由具有端口带宽的应用处理器端口传递到应用处理器。多端口设备包括具有用于存储帧的接收缓冲器大小并且向应用处理器提供帧以进行处理的应用接收缓冲器。提供了可编程逻辑单元，用于监视接收缓冲器中的数据级别并监视转发到所述应用处理器的帧的类型。这些帧每个都具有与其相关联的discriptor帧与指示优先级状态和广播/单播状态中的一个或多个的数据。逻辑单元基于用于在所述接收缓冲器中的数据级别达到具有状态的阈值级别的丢弃帧的至少一个阈值级别来监视数据级别。状态是优先级状态和广播/单播状态中的一种或多种状态。

7. 发明授权

US06246690B1 Method and device for controlling data flow in a computer data network 失效
标题翻译：用于控制计算机数据网络中的数据流的方法和装置
公开(公告)号：US06246690B1
公开(公告)日：2001-06-12
申请号：US09044771
申请日：1998-03-19
申请人： Bruno DiPlacido , Lawrence A. Boxer
发明人： Bruno DiPlacido , Lawrence A. Boxer
IPC分类号： H04L1256
CPC分类号： H04Q11/0478
摘要： An Ethernet flow control system, preferably for a Ethernet switch, having flow controlled transmitting ports in compliance with IEEE Standard 802.3x. The flow control system includes a shared resource, a plurality of buffers receiving data frames from the shared resource, and a plurality of transmitting ports. Each transmitting port being associated with one of the plurality of buffers and being flow controllable between an enabled state and a blocked state. The transmitting port removing and transmitting data frames from the associated buffer when in the enabled state. Each transmitting port including a timer for measuring the time that an associated buffer has a data frame and the corresponding transmitting port is in the blocked state. Each port also includes control logic for removing data frames from the associated buffer when the measured time is greater than a predetermined time.
摘要翻译：以太网流控制系统，优选地用于以太网交换机，具有符合IEEE标准802.3x的流控发送端口。流控制系统包括共享资源，从共享资源接收数据帧的多个缓冲器和多个发送端口。每个发送端口与多个缓冲器中的一个相关联，并且在启用状态和阻塞状态之间可流动地控制。当处于使能状态时，发送端口从相关联的缓冲器中移除和发送数据帧。每个发送端口包括用于测量相关联的缓冲器具有数据帧并且相应的发送端口处于阻塞状态的时间的定时器。每个端口还包括用于当测量时间大于预定时间时从相关联的缓冲器中移除数据帧的控制逻辑。

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