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1. 发明授权

US06528799B1 Device and method for suppressing space charge induced aberrations in charged-particle projection lithography systems 有权
标题翻译：用于抑制带电粒子投影光刻系统中的空间电荷诱导像差的装置和方法
公开(公告)号：US06528799B1
公开(公告)日：2003-03-04
申请号：US09692150
申请日：2000-10-20
申请人： Victor Katsap , James A. Liddle , Masis Mkrtchyan , Stuart T. Stanton
发明人： Victor Katsap , James A. Liddle , Masis Mkrtchyan , Stuart T. Stanton
IPC分类号： H01J37063
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/065 , H01J37/153 , H01J37/3174 , H01J2237/0656 , Y10S977/881 , Y10S977/887
摘要： An electron beam lithographic apparatus has an electron gun providing a beam of accelerated electrons, a mask stage adapted to hold a mask in a path of the beam of accelerated electrons, and a workpiece stage adapted to hold a workpiece in a path of electrons that have passed through the mask. The electron gun has a cathode having an electron emission surface, an anode adapted to be connected to a high-voltage power supply to provide an electric field between the cathode and the anode to accelerate electrons emitted from the cathode toward the anode, and a current-density-profile control grid disposed between the anode and the cathode. The current-density-profile control grid is configured to provide an electron gun that produces an electron beam having a non-uniform current density profile. A method of producing a micro-device includes generating a beam of charged particles having a non-uniform charged-particle current density, illuminating a mask with the beam of charged particles, and exposing a workpiece with charged particles from the beam of charged particles.
摘要翻译：电子束光刻设备具有提供加速电子束的电子枪，适于将加速电子束的路径中的掩模保持的掩模台，以及适于将工件保持在具有穿过面具。电子枪具有具有电子发射表面的阴极，适于连接到高压电源的阳极，以在阴极和阳极之间提供电场，以加速从阴极向阳极发射的电子，以及电流设置在阳极和阴极之间的密度分布控制网格。电流密度分布控制网格被配置为提供产生具有不均匀电流密度分布的电子束的电子枪。微型器件的制造方法包括：生成具有不均匀带电粒子电流密度的带电粒子束，用带电粒子束照射掩模，以及从带电粒子束带电的带电粒子露出工件。

2. 发明授权

US06977128B2 Multi-layered semiconductor structure 失效
标题翻译：多层半导体结构
公开(公告)号：US06977128B2
公开(公告)日：2005-12-20
申请号：US10704449
申请日：2003-11-07
申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
发明人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
IPC分类号： G03F7/20 , G03F9/00 , H01J37/304 , H01J37/305 , H01L21/027 , H01L23/544 , G03C5/00
CPC分类号： H01J37/3045 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S430/143 , Y10S438/975 , H01L2924/00
摘要： A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要翻译：一种多层半导体结构，其具有用于对准光刻掩模并且可以与SCALPEL工具结合使用的对准特征。本发明特别适用于亚微米CMOS工艺器件和电路，但不限于此。本发明有利地允许使用电子束源用于半导体晶片上的光刻掩模的对准和曝光。本发明还有利地使得能够在半导体器件制造工艺中早期（即零电平）形成对准特征。

3. 发明授权

US6015644A Process for device fabrication using a variable transmission aperture 有权
标题翻译：使用可变传输孔径的器件制造工艺
公开(公告)号：US6015644A
公开(公告)日：2000-01-18
申请号：US190351
申请日：1998-11-12
申请人： Raymond Andrew Cirelli , Masis Mkrtchyan , Lee Edward Trimble , George Patrick Watson , David Lee Windt
发明人： Raymond Andrew Cirelli , Masis Mkrtchyan , Lee Edward Trimble , George Patrick Watson , David Lee Windt
IPC分类号： H01L21/027 , G03F7/20 , G03F9/00
CPC分类号： G03F7/705 , G03F7/70091 , G03F7/70191
摘要： A process for device fabrication is disclosed. In the process, optical lithography is used to introduce an image of a desired pattern into an energy sensitive material. In the process, a filter element is provided. The filter element has at least two regions of different transmittance, each region denominated an aperture. The regions are selected by obtaining information about the desired pattern and an optical lithographic tool that will be used to introduce the image of the desired pattern into the energy sensitive resist material. A filter element that provides an image that, when developed, will provide features with dimensions within acceptable process tolerances is then designed. The filter element is designed by modeling the effects of each aperture of the filter element on the intensity profile of an image of the desired pattern. The combined effect of the apertures is then determined. If required, an aspect (transmittance, orientation, dimension) of the one or more of the proposed apertures is adjusted to provide a modeled intensity profile that more closely corresponds to the desired lithographic result. Once the aspects of all apertures is determined, the filter element is fabricated and used in the optical lithographic process by placing the filter element in the optical lithography tool.
摘要翻译：公开了一种用于器件制造的工艺。在该过程中，使用光学光刻技术将期望图案的图像引入到能量敏感材料中。在该过程中，提供过滤元件。滤光元件具有不同透射率的至少两个区域，每个区域指定孔径。通过获得关于期望图案的信息和将用于将期望图案的图像引入能量敏感抗蚀剂材料的光学光刻工具来选择区域。然后设计一种过滤元件，其提供在开发时将提供尺寸在可接受的工艺公差内的特征的图像。过滤器元件通过对滤波器元件的每个孔的影响对期望图案的图像的强度分布进行建模来设计。然后确定孔的组合效果。如果需要，调整所提出的一个或多个孔的一个方面（透射率，取向，尺寸）以提供更接近于所需光刻结果的建模强度分布。一旦确定了所有孔的方面，则通过将滤光元件放置在光刻工具中，在光学平版印刷工艺中制造和使用滤光元件。

4. 发明授权

US06706609B2 Method of forming an alignment feature in or on a multi-layered semiconductor structure 有权
标题翻译：在多层半导体结构中或其上形成取向特征的方法
公开(公告)号：US06706609B2
公开(公告)日：2004-03-16
申请号：US09867202
申请日：2001-05-29
申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
发明人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
IPC分类号： H01L21308
CPC分类号： H01J37/3045 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S430/143 , Y10S438/975 , H01L2924/00
摘要： A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要翻译：一种形成具有用于对准光刻掩模并且可以与SCALPEL工具结合使用的对准特征的多层半导体结构的方法。本发明特别适用于亚微米CMOS工艺器件和电路，但不限于此。本发明有利地允许使用电子束源用于半导体晶片上的光刻掩模的对准和曝光。本发明还有利地使得能够在半导体器件制造工艺中早期（即零电平）形成对准特征。

5. 发明授权

US06576529B1 Method of forming an alignment feature in or on a multilayered semiconductor structure 有权
标题翻译：在多层半导体结构中或其上形成取向特征的方法
公开(公告)号：US06576529B1
公开(公告)日：2003-06-10
申请号：US09456224
申请日：1999-12-07
申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
发明人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
IPC分类号： H01L23544
CPC分类号： H01J37/3045 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S430/143 , Y10S438/975 , H01L2924/00
摘要： A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要翻译：一种形成具有用于对准光刻掩模并且可以与SCALPEL工具结合使用的对准特征的多层半导体结构的方法。本发明特别适用于亚微米CMOS工艺器件和电路，但不限于此。本发明有利地允许使用电子束源用于半导体晶片上的光刻掩模的对准和曝光。本发明还有利地使得能够在半导体器件制造工艺中早期（即零电平）形成对准特征。

6. 发明授权

US5824441A Lithographic process for device fabrication utilizing back-scattered electron beam signal intensity for alignment 失效
标题翻译：利用背散射电子束信号强度进行对准的器件制造的平版印刷工艺
公开(公告)号：US5824441A
公开(公告)日：1998-10-20
申请号：US753855
申请日：1996-12-03
申请人： Reginald Conway Farrow , Masis Mkrtchyan
发明人： Reginald Conway Farrow , Masis Mkrtchyan
IPC分类号： G03F7/20 , H01J37/304 , G03F9/00
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , G03F7/2059 , H01J37/3045 , H01J2237/24475 , H01J2237/3175 , Y10S430/143
摘要： The present invention is directed to a lithographic process for device fabrication. In lithographic processes for device fabrication, exposing radiation is used to delineate the image of a pattern into a layer of an energy sensitive resist material formed over a substrate. The pattern is then developed and the pattern is introduced into the underlying substrate. In the present invention, the substrate, typically a silicon wafer, is placed in a tool which utilizes electron beams as the exposing radiation. The silicon wafer has topographic alignment marks formed thereon. The alignment marks are used to orient the wafer in the tool accurately. The placement of the wafer in the tool is monitored by observing the intensity of the electron signal backscattered from the surface of the substrate. The alignment mark configuration is selected to provide a desired contrast between the intensity of the backscattered electron signal in the aligned state and the intensity of backscattered electron signal in the non-aligned state. The alignment mark dimensions that provide the desired contrast for a given intensity of incident electrons are selected by determining a relationship between backscattered electron signal contrast as a function of a dimensionless parameter that is the ratio of an alignment mark dimension (h) to the range (R) of the scattered electrons in the substrate. From this relationship, the desired backscattered electron signal contrast is selected. The value of the dimensionless parameter that corresponds to this data point is then used to determine the alignment mark dimension that will provide the desired backscattered electron signal contrast.
摘要翻译：本发明涉及用于器件制造的光刻工艺。在用于器件制造的光刻工艺中，暴露辐射用于将图案的图像描绘成在衬底上形成的能量敏感的抗蚀剂材料的层。然后形成图案，并将图案引入到底层基底中。在本发明中，将基板（通常为硅晶片）放置在利用电子束作为曝光辐射的工具中。硅晶片具有在其上形成的地形对准标记。对准标记用于精确地定位工具中的晶片。通过观察从衬底的表面反向散射的电子信号的强度来监测晶片在工具中的放置。选择对准标记配置以提供在对准状态下的后向散射电子信号的强度与处于非对准状态的反向散射电子信号的强度之间的期望的对比度。通过确定反向散射电子信号对比度作为无量纲参数的函数来选择给定强度的入射电子提供期望对比度的对准标记尺寸，该无量纲参数是对准标记尺寸（h）与范围（ R）衬底中的散射电子。根据该关系，选择期望的背散射电子信号对比度。然后使用与该数据点相对应的无量纲参数的值来确定将提供期望的背散射电子信号对比度的对准标记尺寸。

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