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1. 发明授权

US08250308B2 Cache coherency protocol with built in avoidance for conflicting responses 失效
标题翻译：缓存一致性协议内置避免冲突的响应
公开(公告)号：US08250308B2
公开(公告)日：2012-08-21
申请号：US12031977
申请日：2008-02-15
申请人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.
摘要翻译：该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

2. 发明申请

US20090210626A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR CACHE COHERENCY PROTOCOL WITH BUILT IN AVOIDANCE FOR CONFLICTING RESPONSES 失效
标题翻译：用于缓解冲突反应的高速缓存协议的方法，系统和计算机程序产品
公开(公告)号：US20090210626A1
公开(公告)日：2009-08-20
申请号：US12031977
申请日：2008-02-15
申请人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, JR. , Craig R. Waters
发明人： Vesselina K. Papazova , Ekaterina M. Ambroladze , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, JR. , Craig R. Waters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership slate of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.
摘要翻译：该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及指定地址的所有权，将目标行的状态返回到请求节点并形成组合的响应，并将组合的响应广播到每个远程节点。在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

3. 发明授权

US07934059B2 Method, system and computer program product for preventing lockout and stalling conditions in a multi-node system with speculative memory fetching 有权
标题翻译：方法，系统和计算机程序产品，用于防止具有推测性内存提取的多节点系统中的锁定和停顿条件
公开(公告)号：US07934059B2
公开(公告)日：2011-04-26
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

4. 发明申请

US20090193198A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PREVENTING LOCKOUT AND STALLING CONDITIONS IN A MULTI-NODE SYSTEM WITH SPECULATIVE MEMORY FETCHING 有权
标题翻译：方法，系统和计算机程序产品，用于在具有分析存储器故障的多节点系统中防止闭锁和停放条件
公开(公告)号：US20090193198A1
公开(公告)日：2009-07-30
申请号：US12021781
申请日：2008-01-29
申请人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
发明人： Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak , Arthur J. O'Neill, Jr. , Craig R. Waters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.
摘要翻译：一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到解决冲突的点，而不发出另一个推测性的内存提取请求。随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

5. 发明授权

US08990507B2 Storing data in a system memory for a subsequent cache flush 有权
公开(公告)号：US08990507B2
公开(公告)日：2015-03-24
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.

6. 发明申请

US20110314228A1 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：维持多节点对称多处理计算机中的缓存一致性
公开(公告)号：US20110314228A1
公开(公告)日：2011-12-22
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

7. 发明申请

US20080071990A1 Method for Ensuring Fairness Among Requests Within a Multi-Node Computer System 有权
标题翻译：确保多节点计算机系统内的请求之间公平的方法
公开(公告)号：US20080071990A1
公开(公告)日：2008-03-20
申请号：US11532156
申请日：2006-09-15
申请人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
发明人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译：使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止成功了通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否资源有效，但在请求完成之前遇到一些需要解决的冲突。只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成请求被允许进入系统。

8. 发明授权

US08762651B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中维护高速缓存一致性
公开(公告)号：US08762651B2
公开(公告)日：2014-06-24
申请号：US12821578
申请日：2010-06-23
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

9. 发明申请

US20130339613A1 STORING DATA IN A SYSTEM MEMORY FOR A SUBSEQUENT CACHE FLUSH 有权
标题翻译：存储用于后续缓存的系统存储器中的数据
公开(公告)号：US20130339613A1
公开(公告)日：2013-12-19
申请号：US13495383
申请日：2012-06-13
申请人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
发明人： Michael A. Blake , Pak-Kin Mak , Timothy C. Bronson , Hieu T. Huynh , Kenneth D. Klapproth , Vesselina K. Papazova
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0804 , G06F12/0817 , G06F12/0891 , G06F12/128
摘要： Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
摘要翻译：实施例涉及将数据存储到系统存储器。一个方面包括通过步进引擎访问具有多个目录条目的高速缓存目录的连续条目，其中对高速缓存目录的访问被给予比其他高速缓存操作更低的优先级。确定高速缓存目录中的特定目录条目具有指示其被修改的改变行状态。执行存储操作以将特定对应的高速缓存条目的副本作为高速缓存管理功能的一部分发送到系统存储器。特定目录条目被更新以指示改变线状态是未修改的。

10. 发明授权

US08423736B2 Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中维护高速缓存一致性
公开(公告)号：US08423736B2
公开(公告)日：2013-04-16
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

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