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1. 发明授权

US06768155B2 Circuit with buried strap including liner 失效
标题翻译：电路与埋藏带包括衬垫
公开(公告)号：US06768155B2
公开(公告)日：2004-07-27
申请号：US10438352
申请日：2003-05-14
申请人： Venkatachalam C. JaiPrakash , Rajiv Ranade
发明人： Venkatachalam C. JaiPrakash , Rajiv Ranade
IPC分类号： H01L2976
CPC分类号： H01L27/10867 , H01L27/10864
摘要： Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.
摘要翻译：具有其中具有掩埋带的沟槽的半导体器件防止掺杂剂的侧向扩散，以及制造这种半导体器件的方法。

2. 发明授权

US06605504B1 Method of manufacturing circuit with buried strap including a liner 有权
标题翻译：具有包括衬垫的埋设带的电路的制造方法
公开(公告)号：US06605504B1
公开(公告)日：2003-08-12
申请号：US10186043
申请日：2002-06-28
申请人： Venkatachalam C. JaiPrakash , Rajiv Ranade
发明人： Venkatachalam C. JaiPrakash , Rajiv Ranade
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10864
摘要： Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.
摘要翻译：具有其中具有埋置带的沟槽的半导体器件防止了掺杂剂的侧向扩散，以及制造这种半导体器件的方法。

3. 发明申请

US20050051820A1 Fabrication process for a magnetic tunnel junction device 失效
标题翻译：磁性隧道结装置的制造工艺
公开(公告)号：US20050051820A1
公开(公告)日：2005-03-10
申请号：US10659136
申请日：2003-09-10
申请人： George Stojakovic , Rajiv Ranade , Ihar Kasko , Joachim Nuetzel , Keith Milkove , Russell Allen , Young Lee , Kim Lee
发明人： George Stojakovic , Rajiv Ranade , Ihar Kasko , Joachim Nuetzel , Keith Milkove , Russell Allen , Young Lee , Kim Lee
IPC分类号： G11C11/22 , H01L21/00 , H01L27/22 , H01L29/76 , H01L31/062 , H01L31/119 , H01L43/08 , H01L43/12
CPC分类号： G11C11/22 , H01L27/222 , H01L43/12
摘要： A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.
摘要翻译：提供了一种制造磁性隧道结（MTJ）装置的方法。图案化的硬掩模被氧化以在其上形成表面氧化物。在图案化的硬掩模的氧化之后，将MTJ堆叠与图案化的硬掩模对准地蚀刻。优选地，MTJ堆叠蚀刻配方包括氯和氧。硬掩模和MTJ叠层之间的蚀刻选择性得到改善。

4. 发明授权

US06809005B2 Method to fill deep trench structures with void-free polysilicon or silicon 失效
标题翻译：用无孔多晶硅或硅填充深沟槽结构的方法
公开(公告)号：US06809005B2
公开(公告)日：2004-10-26
申请号：US10386880
申请日：2003-03-12
申请人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
发明人： Rajiv Ranade , Gangadhara S. Mathad , Kevin K. Chan , Subhash B. Kulkarni
IPC分类号： H01L2176
CPC分类号： H01L27/1087 , H01L21/0237 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/763 , H01L29/66181
摘要： The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
摘要翻译：本发明提供了在其中制造基本上无空隙填料的沟槽结构的方法。填料可以从诸如沿沟槽的侧壁形成的多晶硅的衬垫材料生长。先前形成的空隙可以通过暴露空隙和生长外延硅来治愈。

5. 发明授权

US6103585A Method of forming deep trench capacitors 失效
标题翻译：形成深沟槽电容器的方法
公开(公告)号：US6103585A
公开(公告)日：2000-08-15
申请号：US93801
申请日：1998-06-09
申请人： Alexander Michaelis , Rajiv Ranade , Bertrand Flietner
发明人： Alexander Michaelis , Rajiv Ranade , Bertrand Flietner
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3065 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10861 , H01L21/30655 , H01L28/40 , H01L29/66181
摘要： A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.
摘要翻译：用于形成DRAM的存储电容器的用于形成DRAM的存储电容器的硅晶片中的垂直沟槽通过反应离子蚀刻以具有多个腰部的轮廓的方式进行蚀刻。通过在反应离子蚀刻期间改变在其上支撑硅晶片的基底构件中的冷却剂的流动速率来获得该轮廓，以在蚀刻期间改变硅晶片的温度。或者，通过改变蚀刻室中的不同气体的比例或室内的总气体压力来实现多个腰部。

6. 发明申请

US20080032428A1 METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS 失效
标题翻译：用于线性尺寸控制的方法和系统
公开(公告)号：US20080032428A1
公开(公告)日：2008-02-07
申请号：US11872098
申请日：2007-10-15
申请人： Gary Behm , Teresita Magtoto , Rajiv Ranade
发明人： Gary Behm , Teresita Magtoto , Rajiv Ranade
IPC分类号： H01L21/66
CPC分类号： H01J37/32082 , H01J37/32935
摘要： A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.
摘要翻译：一种用于控制蚀刻特征尺寸的方法和系统。该方法包括：测量形成在基板上的层的顶表面上的掩模特征以获得掩模特征尺寸值; 以及基于掩模特征尺寸值，掩模特征尺寸目标值，等离子体蚀刻工具的选定的射频加电时间的总和，计算掩模修整等离子体蚀刻时间，因为发生到等离子体的室或室的事件用于等离子体蚀刻该层的蚀刻工具，以及用于在该层的等离子体蚀刻期间该层不被掩模特征保护的层形成的层特征的蚀刻偏置目标。

7. 发明申请

US20060255010A1 Method and system for line-dimension control of an etch process 有权
标题翻译：用于蚀刻工艺的线尺寸控制的方法和系统
公开(公告)号：US20060255010A1
公开(公告)日：2006-11-16
申请号：US11125696
申请日：2005-05-10
申请人： Gary Behm , Teresita Magtoto , Rajiv Ranade
发明人： Gary Behm , Teresita Magtoto , Rajiv Ranade
IPC分类号： G01L21/30 , C23F1/00
CPC分类号： H01J37/32082 , H01J37/32935
摘要： A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.
摘要翻译：一种用于控制蚀刻特征尺寸的方法和系统。该方法包括：测量形成在基板上的层的顶表面上的掩模特征以获得掩模特征尺寸值; 以及基于掩模特征尺寸值，掩模特征尺寸目标值，等离子体蚀刻工具的选定的射频加电时间的总和，计算掩模修整等离子体蚀刻时间，因为发生到等离子体的室或室的事件用于等离子体蚀刻该层的蚀刻工具，以及用于在该层的等离子体蚀刻期间该层不被掩模特征保护的层形成的层特征的蚀刻偏置目标。

8. 发明申请

US20050260859A1 METHOD FOR PATTERNING A SEMICONDUCTOR REGION 失效
标题翻译：用于绘制半导体区域的方法
公开(公告)号：US20050260859A1
公开(公告)日：2005-11-24
申请号：US10709673
申请日：2004-05-21
申请人： Sadanand Deshpande , Rajiv Ranade , George Worth
发明人： Sadanand Deshpande , Rajiv Ranade , George Worth
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/461 , H01L29/49
CPC分类号： H01L21/28035 , H01L21/32137 , H01L29/4925
摘要： A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.
摘要翻译：提供了可以重掺杂的半导体区域图形化的方法。在半导体区域上方设置图案化掩模。通过图案化掩模曝光的半导体区域的一部分在包括聚合碳氟化合物，例如碳与氟原子比高的无氯碳氟化合物的环境中被蚀刻，以及至少一种选自下组的非聚合物质由非聚合碳氟化合物组成，例如碳与氟原子比低的氢化碳氟化合物。该方法优选地钝化图案化的半导体区域的侧壁，使得可以在图案化区域下方的半导体材料的下部区域被定向蚀刻，而不会侵蚀如此钝化的图案化区域。

9. 发明授权

US06544838B2 Method of deep trench formation with improved profile control and surface area 失效
公开(公告)号：US06544838B2
公开(公告)日：2003-04-08
申请号：US09805071
申请日：2001-03-13
申请人： Rajiv Ranade , Munir D. Naeem , Gangadhara S. Mathad
发明人： Rajiv Ranade , Munir D. Naeem , Gangadhara S. Mathad
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3065 , H01L21/3081
摘要： A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.

10. 发明申请

US20070056927A1 Process and system for etching doped silicon 审中-公开
标题翻译：蚀刻掺杂硅的工艺和系统
公开(公告)号：US20070056927A1
公开(公告)日：2007-03-15
申请号：US11225893
申请日：2005-09-14
申请人： Len Tsou , Rajiv Ranade , George Kaplita , Hongwen Yan , Rich Wise , Akiteru Ko
发明人： Len Tsou , Rajiv Ranade , George Kaplita , Hongwen Yan , Rich Wise , Akiteru Ko
IPC分类号： C23F1/00 , G05B21/00 , H01L21/306 , B44C1/22
CPC分类号： H01L21/32137 , H01L21/28035 , H01L21/28123 , H01L21/67069
摘要： A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises a nitrogen containing gas and a fluorocarbon gas. For example, the process chemistry comprises CF4, C4F8 and N2.
摘要翻译：描述了通过掺杂硅层的各向异性干蚀刻的工艺和系统。工艺化学品包括含氮气体和碳氟化合物气体。例如，该方法的化学性质包括CF 4，C 4 H 8和N 2。

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