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1. 发明申请

US20080032428A1 METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS 失效
标题翻译：用于线性尺寸控制的方法和系统
公开(公告)号：US20080032428A1
公开(公告)日：2008-02-07
申请号：US11872098
申请日：2007-10-15
申请人： Gary Behm , Teresita Magtoto , Rajiv Ranade
发明人： Gary Behm , Teresita Magtoto , Rajiv Ranade
IPC分类号： H01L21/66
CPC分类号： H01J37/32082 , H01J37/32935
摘要： A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.
摘要翻译：一种用于控制蚀刻特征尺寸的方法和系统。该方法包括：测量形成在基板上的层的顶表面上的掩模特征以获得掩模特征尺寸值; 以及基于掩模特征尺寸值，掩模特征尺寸目标值，等离子体蚀刻工具的选定的射频加电时间的总和，计算掩模修整等离子体蚀刻时间，因为发生到等离子体的室或室的事件用于等离子体蚀刻该层的蚀刻工具，以及用于在该层的等离子体蚀刻期间该层不被掩模特征保护的层形成的层特征的蚀刻偏置目标。

2. 发明申请

US20060255010A1 Method and system for line-dimension control of an etch process 有权
标题翻译：用于蚀刻工艺的线尺寸控制的方法和系统
公开(公告)号：US20060255010A1
公开(公告)日：2006-11-16
申请号：US11125696
申请日：2005-05-10
申请人： Gary Behm , Teresita Magtoto , Rajiv Ranade
发明人： Gary Behm , Teresita Magtoto , Rajiv Ranade
IPC分类号： G01L21/30 , C23F1/00
CPC分类号： H01J37/32082 , H01J37/32935
摘要： A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.
摘要翻译：一种用于控制蚀刻特征尺寸的方法和系统。该方法包括：测量形成在基板上的层的顶表面上的掩模特征以获得掩模特征尺寸值; 以及基于掩模特征尺寸值，掩模特征尺寸目标值，等离子体蚀刻工具的选定的射频加电时间的总和，计算掩模修整等离子体蚀刻时间，因为发生到等离子体的室或室的事件用于等离子体蚀刻该层的蚀刻工具，以及用于在该层的等离子体蚀刻期间该层不被掩模特征保护的层形成的层特征的蚀刻偏置目标。

3. 发明申请

US20050260859A1 METHOD FOR PATTERNING A SEMICONDUCTOR REGION 失效
标题翻译：用于绘制半导体区域的方法
公开(公告)号：US20050260859A1
公开(公告)日：2005-11-24
申请号：US10709673
申请日：2004-05-21
申请人： Sadanand Deshpande , Rajiv Ranade , George Worth
发明人： Sadanand Deshpande , Rajiv Ranade , George Worth
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/461 , H01L29/49
CPC分类号： H01L21/28035 , H01L21/32137 , H01L29/4925
摘要： A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.
摘要翻译：提供了可以重掺杂的半导体区域图形化的方法。在半导体区域上方设置图案化掩模。通过图案化掩模曝光的半导体区域的一部分在包括聚合碳氟化合物，例如碳与氟原子比高的无氯碳氟化合物的环境中被蚀刻，以及至少一种选自下组的非聚合物质由非聚合碳氟化合物组成，例如碳与氟原子比低的氢化碳氟化合物。该方法优选地钝化图案化的半导体区域的侧壁，使得可以在图案化区域下方的半导体材料的下部区域被定向蚀刻，而不会侵蚀如此钝化的图案化区域。

4. 发明授权

US06544838B2 Method of deep trench formation with improved profile control and surface area 失效
公开(公告)号：US06544838B2
公开(公告)日：2003-04-08
申请号：US09805071
申请日：2001-03-13
申请人： Rajiv Ranade , Munir D. Naeem , Gangadhara S. Mathad
发明人： Rajiv Ranade , Munir D. Naeem , Gangadhara S. Mathad
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3065 , H01L21/3081
摘要： A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.

5. 发明申请

US20070056927A1 Process and system for etching doped silicon 审中-公开
标题翻译：蚀刻掺杂硅的工艺和系统
公开(公告)号：US20070056927A1
公开(公告)日：2007-03-15
申请号：US11225893
申请日：2005-09-14
申请人： Len Tsou , Rajiv Ranade , George Kaplita , Hongwen Yan , Rich Wise , Akiteru Ko
发明人： Len Tsou , Rajiv Ranade , George Kaplita , Hongwen Yan , Rich Wise , Akiteru Ko
IPC分类号： C23F1/00 , G05B21/00 , H01L21/306 , B44C1/22
CPC分类号： H01L21/32137 , H01L21/28035 , H01L21/28123 , H01L21/67069
摘要： A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises a nitrogen containing gas and a fluorocarbon gas. For example, the process chemistry comprises CF4, C4F8 and N2.
摘要翻译：描述了通过掺杂硅层的各向异性干蚀刻的工艺和系统。工艺化学品包括含氮气体和碳氟化合物气体。例如，该方法的化学性质包括CF 4，C 4 H 8和N 2。

6. 发明申请

US20050009295A1 Novel method to achieve increased trench depth, independent of CD as defined by lithography 失效
标题翻译：实现增加沟槽深度的新方法，与光刻所定义的CD无关
公开(公告)号：US20050009295A1
公开(公告)日：2005-01-13
申请号：US10899758
申请日：2004-07-27
申请人： Kevin Chan , Subhash Kulkarni , Gangadhara Mathad , Rajiv Ranade
发明人： Kevin Chan , Subhash Kulkarni , Gangadhara Mathad , Rajiv Ranade
IPC分类号： H01L21/308 , H01L21/762 , H01L21/768 , H01L21/8242 , H01L21/76
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/76224 , H01L21/76895
摘要： A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.
摘要翻译：提供了形成具有增加的沟槽深度的至少一个深沟槽结构的方法。该方法包括提供至少一个具有延伸到衬底表面中的公共底壁的侧壁的深沟槽。每个深沟槽的初始尺寸比深沟槽的目标尺寸宽。为了将初始尺寸减小到目标尺寸的尺寸，使用低温超高真空外延硅生长技术在侧壁的至少一些部分上选择性地或非选择性地形成外延硅膜。

7. 发明授权

US06821900B2 Method for dry etching deep trenches in a substrate 失效
标题翻译：干法蚀刻衬底深沟的方法
公开(公告)号：US06821900B2
公开(公告)日：2004-11-23
申请号：US09757123
申请日：2001-01-09
申请人： Satish Athavale , Rajiv Ranade , Munir Naeem , Gangadhara Swami Mathad
发明人： Satish Athavale , Rajiv Ranade , Munir Naeem , Gangadhara Swami Mathad
IPC分类号： H01L21311
CPC分类号： H01L21/3065 , H01L21/32136 , H01L21/32137
摘要： A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.
摘要翻译：用于蚀刻衬底中的沟槽的方法将晶片固定到等离子体室中的电极，并将晶片加热到大于200摄氏度的温度。将晶片暴露于反应等离子体，以最小的蚀刻副产物再沉积来将沟槽蚀刻到晶片的衬底中，以避免夹住沟槽并促进进一步蚀刻。

8. 发明授权

US06768155B2 Circuit with buried strap including liner 失效
标题翻译：电路与埋藏带包括衬垫
公开(公告)号：US06768155B2
公开(公告)日：2004-07-27
申请号：US10438352
申请日：2003-05-14
申请人： Venkatachalam C. JaiPrakash , Rajiv Ranade
发明人： Venkatachalam C. JaiPrakash , Rajiv Ranade
IPC分类号： H01L2976
CPC分类号： H01L27/10867 , H01L27/10864
摘要： Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.
摘要翻译：具有其中具有掩埋带的沟槽的半导体器件防止掺杂剂的侧向扩散，以及制造这种半导体器件的方法。

9. 发明授权

US06605504B1 Method of manufacturing circuit with buried strap including a liner 有权
标题翻译：具有包括衬垫的埋设带的电路的制造方法
公开(公告)号：US06605504B1
公开(公告)日：2003-08-12
申请号：US10186043
申请日：2002-06-28
申请人： Venkatachalam C. JaiPrakash , Rajiv Ranade
发明人： Venkatachalam C. JaiPrakash , Rajiv Ranade
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10864
摘要： Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.
摘要翻译：具有其中具有埋置带的沟槽的半导体器件防止了掺杂剂的侧向扩散，以及制造这种半导体器件的方法。

10. 发明授权

US06489249B1 Elimination/reduction of black silicon in DT etch 有权
标题翻译：在DT蚀刻中消除/还原黑色硅
公开(公告)号：US06489249B1
公开(公告)日：2002-12-03
申请号：US09597441
申请日：2000-06-20
申请人： Gangadhara S. Mathad , Rajiv Ranade
发明人： Gangadhara S. Mathad , Rajiv Ranade
IPC分类号： H01L2100
CPC分类号： H01J37/32623 , H01J37/32642 , H01L21/3065 , Y10S156/915
摘要： In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of the etch chamber, to provide extension of a Vdc flat sheath boundary beyond and into a defocusing relationship to the wafer edge to reduce mask erosion and eliminate occurrence of “black silicon” formation.
摘要翻译：在蚀刻等离子体蚀刻反应器中的晶片的方法中，改进导电蚀刻以减少或消除“黑硅”，包括：a）提供包含限定蚀刻室的壁的等离子体蚀刻反应器; b）提供等离子体源室远离提供等离子体到蚀刻室，以及设置在蚀刻室中以安置晶片的晶片卡盘或基座; c）在晶片的周边附近和周围提供电介质壁; d）通过将导体装置插入到电介质壁装置和晶片的Vdc平面鞘边界关系的延伸部中或代替电介质壁来提供对下部Rf电极的修改; e）在等离子体源室内形成等离子体;以及将等离子体提供给蚀刻室; 以及f）通过在晶片的上表面和蚀刻室的壁之间形成电场来提供晶片卡盘的Rf能量以辅助晶片的蚀刻，以提供超过Vdc平坦护套边界超过和散焦关系的Vdc 晶圆边缘减少掩模侵蚀，消除“黑硅”形成的发生。

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