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1. 发明申请

US20130164890A1 METHOD FOR FABRICATING FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：用合适的FINS和垂直硅胶制造FINFET的方法
公开(公告)号：US20130164890A1
公开(公告)日：2013-06-27
申请号：US13617709
申请日：2012-09-14
申请人： Veeraraghavan S. BASKER , Andres BRYANT , Huiming BU , Wilfried HAENSCH , Effendi LEOBANDUNG , Chung-Hsun LIN , Theodorus E. STANDAERT , Tenko YAMASHITA , Chun-chen YEH
发明人： Veeraraghavan S. BASKER , Andres BRYANT , Huiming BU , Wilfried HAENSCH , Effendi LEOBANDUNG , Chung-Hsun LIN , Theodorus E. STANDAERT , Tenko YAMASHITA , Chun-chen YEH
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了一种用于制造finFET器件的方法。翅片结构形成在BOX层上。翅片结构包括半导体层并沿第一方向延伸。栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。栅极堆叠包括高K电介质层和金属栅极。栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

2. 发明申请

US20120292704A1 BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE 有权
标题翻译：障碍物TRENCH结构及其制造方法
公开(公告)号：US20120292704A1
公开(公告)日：2012-11-22
申请号：US13108144
申请日：2011-05-16
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK , Jed H. RANKIN
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK , Jed H. RANKIN
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/762
CPC分类号： H01L27/092 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/0642
摘要： A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with material to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
摘要翻译：一种方法包括在衬底中形成至少一个浅沟槽隔离结构以隔离相邻的不同类型的器件。该方法还包括在衬底中形成阻挡沟槽结构以隔离相邻相同类型器件的扩散。该方法进一步包括将阻挡沟槽结构与材料连接，以将相邻相同类型器件的扩散连接在与相邻相同类型器件相同的水平上。

3. 发明申请

US20120241857A1 DUAL STRESS DEVICE AND METHOD 有权
标题翻译：双应力装置和方法
公开(公告)号：US20120241857A1
公开(公告)日：2012-09-27
申请号：US13492108
申请日：2012-06-08
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力栅结构的区域。

4. 发明申请

US20120188008A1 CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF 有权
标题翻译：具有堆叠结构的电路及其使用
公开(公告)号：US20120188008A1
公开(公告)日：2012-07-26
申请号：US13432565
申请日：2012-03-28
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
IPC分类号： H03H11/24
CPC分类号： H03K19/20
摘要： A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.
摘要翻译：电路具有在堆叠的底部具有至少一个对称FET的堆叠结构。更具体地，该电路具有堆叠结构，其包括不对称FET和对称FET。对称FET放置在层叠结构的底部，比不对称FET更接近地。

5. 发明申请

US20100244139A1 STRAINED-SILICON CMOS DEVICE AND METHOD 审中-公开
标题翻译：应变硅CMOS器件及方法
公开(公告)号：US20100244139A1
公开(公告)日：2010-09-30
申请号：US12797104
申请日：2010-06-09
申请人： Andres BRYANT , Qiqing OUYANG , Kern RIM
发明人： Andres BRYANT , Qiqing OUYANG , Kern RIM
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/7624 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

6. 发明申请

US20110121862A1 CIRCUIT WITH STACKED STRUCTURE AND USE THEREOF 有权
标题翻译：具有堆叠结构的电路及其使用
公开(公告)号：US20110121862A1
公开(公告)日：2011-05-26
申请号：US12626169
申请日：2009-11-25
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
IPC分类号： H03K19/094 , H03H11/24
CPC分类号： H03K19/20
摘要： An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground than the asymmetric FET.
摘要翻译： NAND电路具有在堆叠的底部具有至少一个对称NFET的堆叠结构。更具体地，该电路具有堆叠结构，其包括不对称FET和对称FET。对称FET放置在层叠结构的底部，比不对称FET更接近地。

7. 发明申请

US20110057258A1 DUAL STRESS DEVICE AND METHOD 有权
标题翻译：双应力装置和方法
公开(公告)号：US20110057258A1
公开(公告)日：2011-03-10
申请号：US12875416
申请日：2010-09-03
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力栅结构的区域。

8. 发明申请

US20110278649A1 NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING 有权
标题翻译：像素传感器电极的非均匀栅极电介质电荷及其制造方法
公开(公告)号：US20110278649A1
公开(公告)日：2011-11-17
申请号：US12780193
申请日：2010-05-14
申请人： Brent A. ANDERSON , Andres BRYANT , William F. CLARK, JR. , John J. ELLIS-MONAGHAN , Edward J. NOWAK
发明人： Brent A. ANDERSON , Andres BRYANT , William F. CLARK, JR. , John J. ELLIS-MONAGHAN , Edward J. NOWAK
IPC分类号： H01L31/113 , H01L31/18 , H01L31/14
CPC分类号： H01L31/02 , H01L27/14614 , H01L27/14689
摘要： A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.
摘要翻译：提供了用于像素传感器单元的非均匀栅介质电荷，例如CMOS光学成像器，以及制造方法。该方法包括在衬底上形成栅极电介质。衬底包括源/漏区和光电池收集区。该方法还包括在栅极电介质中形成不均匀的固定电荷分布。该方法还包括在栅极电介质上形成栅极结构。

9. 发明申请

US20110062240A1 DEVICE AND METHOD FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE INDENTIFICATION 有权
标题翻译：用于提供一体化标准的集成电路的装置和方法
公开(公告)号：US20110062240A1
公开(公告)日：2011-03-17
申请号：US12560031
申请日：2009-09-15
申请人： Brent A. ANDERSON , Andres BRYANT , Alain LOISEAU , Anthony K. STAMPER , Mickey H. YU
发明人： Brent A. ANDERSON , Andres BRYANT , Alain LOISEAU , Anthony K. STAMPER , Mickey H. YU
IPC分类号： G06K19/00 , G06K19/067
CPC分类号： G06K19/067 , G06F21/73 , G06F2221/2129
摘要： A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.
摘要翻译：一种用于向集成电路提供唯一标识的装置和方法。该装置可用于产生识别IC的识别（ID）的集成电路（IC），并且包括利用四线电阻器，薄膜电阻器和逆变器对之一的多个识别单元。测量电路测量每个单元的参数，并且用于响应于此生成ID。

10. 发明申请

US20100167504A1 Methods of Fabricating Nanostructures 失效
标题翻译：制造纳米结构的方法
公开(公告)号：US20100167504A1
公开(公告)日：2010-07-01
申请号：US12344696
申请日：2008-12-29
申请人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK , Jeffrey W. SLEIGHT
发明人： Brent A. ANDERSON , Andres BRYANT , Edward J. NOWAK , Jeffrey W. SLEIGHT
IPC分类号： H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/16 , H01L29/161 , Y10S977/888
摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
摘要翻译：示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。该方法还包括分离Si材料以形成硅纳米线。

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