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1. 发明授权

US07796060B2 Circuits and methods to minimize nonlinearity errors in interpolating circuits 有权
标题翻译：最小化内插电路中的非线性误差的电路和方法
公开(公告)号：US07796060B2
公开(公告)日：2010-09-14
申请号：US12188014
申请日：2008-08-07
申请人： Ralph G. Oberhuber , Timothy V. Kalthoff
发明人： Ralph G. Oberhuber , Timothy V. Kalthoff
IPC分类号： H03M13/00
CPC分类号： H03M1/06 , H03M1/0682 , H03M1/682 , H03M1/747 , H03M1/765
摘要： Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.
摘要翻译：这里描述了最小化内插电路中的非线性误差的电路和方法。公开的示例电路包括第一和第二电压 - 电流转换器电路，每个电压 - 电流转换器电路各自包括第一晶体管和第二晶体管，每个具有第一电极，第一电极被配置为接收由相应的电流源产生的信号;第一电流源，第一电压转换器电路，并且包括第一误差校正电路，以通过设置通过第一电流源的第一电流来最小化内插电路中的积分非线性误差，以在标称线性运行模式下操作第一电压转换器电路，以及第二电流源向第二电压转换器电路提供信号，并且包括第二误差校正电路，以通过设置通过第二电流源的第二电流来最小化内插电路中的积分非线性误差，以在额定线性运行中操作第二电压转换器电路模式。

2. 发明申请

US20100033356A1 CIRCUITS AND METHODS TO MINIMIZE NONLINEARITY ERRORS IN INTERPOLATING CIRCUITS 有权
标题翻译：最小化插入电路中非线性误差的电路和方法
公开(公告)号：US20100033356A1
公开(公告)日：2010-02-11
申请号：US12188014
申请日：2008-08-07
申请人： Ralph G. Oberhuber , Timothy V. Kalthoff
发明人： Ralph G. Oberhuber , Timothy V. Kalthoff
IPC分类号： H03M13/00
CPC分类号： H03M1/06 , H03M1/0682 , H03M1/682 , H03M1/747 , H03M1/765
摘要： Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.
摘要翻译：这里描述了最小化内插电路中的非线性误差的电路和方法。公开的示例电路包括第一和第二电压 - 电流转换器电路，每个电压 - 电流转换器电路各自包括第一晶体管和第二晶体管，每个具有第一电极，第一电极被配置为接收由相应的电流源产生的信号;第一电流源，第一电压转换器电路，并且包括第一误差校正电路，以通过设置通过第一电流源的第一电流来最小化内插电路中的积分非线性误差，以在标称线性运行模式下操作第一电压转换器电路，以及第二电流源向第二电压转换器电路提供信号，并且包括第二误差校正电路，以通过设置通过第二电流源的第二电流来最小化内插电路中的积分非线性误差，以在额定线性运行中操作第二电压转换器电路模式。

3. 发明授权

US07047263B2 Fast-settling digital filter and method for analog-to-digital converters 有权
标题翻译：快速建立数字滤波器和模数转换器的方法
公开(公告)号：US07047263B2
公开(公告)日：2006-05-16
申请号：US09929855
申请日：2001-08-14
申请人： James L. Todsen , Ka Y. Leung , Timothy V. Kalthoff
发明人： James L. Todsen , Ka Y. Leung , Timothy V. Kalthoff
IPC分类号： G06F17/17 , G06F17/10
CPC分类号： H03H17/0283
摘要： A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary technique utilizes a composite filter for a faster settling, lower noise resolution filter in a parallel configuration with a slower settling, higher noise resolution filter. As a result, valid data can be received faster for processing by the analog-to-digital converter. In addition, a composite digital filter circuit can include a three filter configuration including a fast-settling, low resolution first filter, a slower-settling, higher resolution second filter, and an even slower-settling, even higher resolution third filter, each of the filters configured in a parallel arrangement. Additional or fewer filters can also be provided. Moreover, the gain of each filter path can be suitably matched to the gain of any other filter path in the digital filter circuit to provide a filter output having an equalized gain regardless of the filter path selected. For example, a filter path can be suitably configured with a multiplier component such that an equalized gain can be realized for each filter path. In addition, the various filters of the digital filter circuit can be configured within the parallel arrangement to provide reduce layout requirements through the sharing of components. For example, a second filter can share at least two integrators with the third filter, and the first filter can share at least one integrator with the third filter. Further, the digital filter can be suitably configured for operation in various industrial applications. For example, the first filter can be suitably configured with a notch filter configured to replace the first, third and other odd harmonic notches of the first filter.
摘要翻译：提供了一种技术和电路，用于促进数字滤波器与模数转换器一起使用的更快的建立时间。一种示例性技术利用复合滤波器用于具有较慢建立的较高噪声分辨率滤波器的并行配置的更快建立的较低噪声分辨率滤波器。因此，可以更快地接收有效数据以供模拟数字转换器处理。此外，复合数字滤波器电路可以包括三滤波器配置，其包括快速稳定，低分辨率第一滤波器，较慢稳定的，较高分辨率的第二滤波器，以及甚至更慢稳定，甚至更高分辨率的第三滤波器，滤波器以并联的方式配置。还可以提供额外的或更少的过滤器。此外，每个滤波器路径的增益可以适当地匹配数字滤波器电路中的任何其它滤波器路径的增益，以提供具有均衡增益的滤波器输出，而不管所选择的滤波器路径如何。例如，滤波器路径可以适当地配置有乘法器组件，使得可以为每个滤波器路径实现均衡的增益。此外，数字滤波器电路的各种滤波器可以在并行布置内配置，以通过共享组件来提供降低的布局要求。例如，第二滤波器可以与第三滤波器共享至少两个积分器，并且第一滤波器可以与第三滤波器共享至少一个积分器。此外，数字滤波器可以适当地构造用于在各种工业应用中操作。例如，第一滤波器可以适当地配置有陷波滤波器，该陷波滤波器被配置为代替第一滤波器的第一，第三和其它奇数谐波陷波。

4. 发明授权

US5691720A Delta sigma analog-to-digital converter having programmable resolution/bias current circuitry and method 失效
标题翻译：具有可编程分辨率/偏置电流电路和方法的Δ西格玛模数转换器
公开(公告)号：US5691720A
公开(公告)日：1997-11-25
申请号：US613112
申请日：1996-03-08
申请人： Binan Wang , Timothy V. Kalthoff , Miaochen Wu
发明人： Binan Wang , Timothy V. Kalthoff , Miaochen Wu
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/392 , H03M3/374 , H03M3/43 , H03M3/454
摘要： Programmable resolution/bias current control circuitry is provided in a delta sigma analog-to-digital converter including an input sampling circuit, a feedback reference sampling circuit, an integrator including an operational amplifier, a comparator, and a digital filter, the input sampling circuit and the feedback reference sampling circuit being coupled to a first input of the operational amplifier, an output of the operational amplifier being coupled to an input of the comparator, an output of the comparator being coupled to an input of the digital filter. The programmable resolution/bias control circuitry includes a clock generator circuit supplying a clock signal to the input sampling circuit and the feedback sampling circuit at a sampling frequency determined by a sampling frequency control signal. A bias current generator circuit supplies a bias current to the operational amplifier to control the settling time of an output step voltage signal produced by the operational amplifier. A control circuit receives a resolution control signal and changes both the sampling frequency control signal and a bias control signal in response to the resolution control signal so as to achieve a predetermined tradeoff between resolution of the digital output and dc power dissipation of the analog-to-digital converter.
摘要翻译：可编程分辨率/偏置电流控制电路在包括输入采样电路，反馈参考采样电路，包括运算放大器，比较器和数字滤波器的积分器的Δ-Σ模数转换器中提供，输入采样电路并且所述反馈参考采样电路耦合到所述运算放大器的第一输入，所述运算放大器的输出耦合到所述比较器的输入，所述比较器的输出耦合到所述数字滤波器的输入端。可编程分辨率/偏置控制电路包括以采样频率控制信号确定的采样频率向输入采样电路和反馈采样电路提供时钟信号的时钟发生器电路。偏置电流发生器电路向运算放大器提供偏置电流以控制由运算放大器产生的输出阶跃电压信号的建立时间。控制电路接收分辨率控制信号，并响应于分辨率控制信号改变采样频率控制信号和偏置控制信号，以便实现数字输出的分辨率与模数转换器的直流功率消耗之间的预定权衡数字转换器

5. 发明授权

US4954769A CMOS voltage reference and buffer circuit 失效
标题翻译： CMOS参考电压和缓冲电路
公开(公告)号：US4954769A
公开(公告)日：1990-09-04
申请号：US308109
申请日：1989-02-08
申请人： Timothy V. Kalthoff
发明人： Timothy V. Kalthoff
IPC分类号： H03F1/26 , G05F1/46 , G05F3/30 , H03F1/30 , H03F3/347
CPC分类号： G05F3/30 , G05F1/467 , H01L2924/0002
摘要： A stable, low noise, low output impedance CMOS reference voltage circuit includes a CMOS/bipolar band gap circuit producing a reference voltage on the source of a source follower transistor driven by an output of a CMOS differential amplifier which maintains a V.sub.THERMAL voltage across the bases of a pair of emitter follower transistors driving the inputs of the CMOS differential amplifier. A power supply noise rejection circuit includes a cascode MOSFET coupling the drain of the source follower output transistor to a positive power supply voltage conductor. A current mirror circuit greatly attenuates any power supply voltage perturbations before they reach the gate of the cascode MOSFET. A unity gain buffer includes a CMOS differential amplifier input stage with one input coupled to the output of the source follower transistor and an output driving a CMOS operational transconductance amplifier.
摘要翻译：稳定，低噪声，低输出阻抗CMOS参考电压电路包括CMOS /双极性带隙电路，其在由CMOS差分放大器的输出驱动的源极跟随器晶体管的源极上产生参考电压，该差分放大器在基极上保持VTHERMAL电压的一对射极跟随器晶体管驱动CMOS差分放大器的输入。电源噪声抑制电路包括将源极跟随器输出晶体管的漏极耦合到正电源电压导体的共源共栅MOSFET。电流镜电路在到达共源共栅MOSFET的栅极之前会大大衰减任何电源电压扰动。单位增益缓冲器包括CMOS差分放大器输入级，其中一个输入耦合到源极跟随器晶体管的输出端和驱动CMOS运算跨导放大器的输出。

6. 发明授权

US06404376B1 Capacitor array having reduced voltage coefficient induced non-linearities 有权
标题翻译：具有降低的电压系数的电容阵列引起的非线性
公开(公告)号：US06404376B1
公开(公告)日：2002-06-11
申请号：US09607475
申请日：2000-06-30
申请人： Timothy V. Kalthoff , Bernd M. Rundel
发明人： Timothy V. Kalthoff , Bernd M. Rundel
IPC分类号： H03M100
CPC分类号： H03M1/0643 , H03M1/468 , H03M1/804
摘要： A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.
摘要翻译：电容器阵列被配置为取消或消除阵列内的电容器的电压系数，从而减小和/或消除存在于A / D转换器内的电压系数非线性。在电容器阵列中，第一电容器适当地配置有阵列中的至少一个附加电容器，使得跨阵列的电荷相对于施加到阵列的输入的输入电压是线性的。此外，第一电容器的电压系数非线性可以通过阵列内的任何附加电容器的反向电压系数非线性来适当地消除，从而降低A / D转换器内的非线性电位。

7. 发明授权

US5703589A Switched capacitor input sampling circuit and method for delta sigma modulator 失效
标题翻译：开关电容输入采样电路和三角Σ调制器的方法
公开(公告)号：US5703589A
公开(公告)日：1997-12-30
申请号：US611329
申请日：1996-03-08
申请人： Timothy V. Kalthoff , Binan Wang , Miaochen Wu
发明人： Timothy V. Kalthoff , Binan Wang , Miaochen Wu
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/34 , H03M3/43 , H03M3/456
摘要： A switched capacitor input sampling circuit in a chopper stabilized delta sigma modulator includes first and second input terminals adapted to receive a differential analog input voltage therebetween and first and second terminals coupled to first and second charge summing conductors, respectively, of the delta sigma modulator. The switched capacitor input sampling circuit also includes a first switch coupled between the first input terminal and a first conductor, a second switch coupled between the second input terminal and a second conductor, a third switch coupled between the first conductor and a bias voltage conductor, a fourth switch coupled between the second conductor and the bias voltage conductor, a first input capacitor coupled between the first conductor and a third conductor, a second input capacitor coupled between the second conductor and a fourth conductor, a fifth switch coupled between the third and fourth conductors, a sixth switch coupled between the third conductor and the first charge summing conductor, and a seventh switch coupled between the fourth conductor and the second charge summing conductor.
摘要翻译：斩波稳定的Δ-Σ调制器中的开关电容器输入采样电路包括适于在其间接收差分模拟输入电压的第一和第二输入端，以及分别耦合到Δ-Σ调制器的第一和第二充电求和导体的第一和第二端子。开关电容器输入采样电路还包括耦合在第一输入端和第一导体之间的第一开关，耦合在第二输入端和第二导体之间的第二开关，耦合在第一导体和偏置电压导体之间的第三开关，耦合在所述第二导体和所述偏置电压导体之间的第四开关，耦合在所述第一导体和第三导体之间的第一输入电容器，耦合在所述第二导体和第四导体之间的第二输入电容器，耦合在所述第三导体和所述第三导体之间的第五开关，第四导体，耦合在第三导体和第一电荷求和导体之间的第六开关，以及耦合在第四导体和第二充电求和导体之间的第七开关。

8. 发明授权

US5103230A Precision digitized current integration and measurement circuit 失效
标题翻译：精密数字电流积分和测量电路
公开(公告)号：US5103230A
公开(公告)日：1992-04-07
申请号：US679556
申请日：1991-04-02
申请人： Timothy V. Kalthoff , Rodney T. Burt
发明人： Timothy V. Kalthoff , Rodney T. Burt
IPC分类号： H03M1/48
CPC分类号： H03M1/48
摘要： A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current. The tracking circuit includes a first integrator having an input coupled to the output of the comparator, a predictor circuit producing average step rate information in response to an output of the first integrator, and a second integrator producing the digital signals in response to the predictor means to produce accurate tracking. The integrating capacitor and digital-to-analog converter are included in a CDAC.
摘要翻译：电流积分模数转换器包括具有耦合到接地电压的非反相输入的比较器和耦合到承载模拟输入电流的输入导体的反相输入。一种积分电容器，其具有耦合到输入导体的一个端子和耦合到数模转换器的输出端的另一端子。跟踪电路耦合到比较器的输出端，以将数字信号施加到数模转换器的输入端，以保持反相输入接近虚拟接地电压。数字滤波器对数字信号进行滤波以产生精确表示输入电流的数字输出信号。跟踪电路包括具有耦合到比较器的输出的输入的第一积分器，响应于第一积分器的输出产生平均步进速率信息的预测器电路，以及响应于预测器装置产生数字信号的第二积分器以产生准确的跟踪。积分电容器和数模转换器包含在CDAC中。

9. 发明授权

US08581770B2 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US08581770B2
公开(公告)日：2013-11-12
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

10. 发明申请

US20120280841A1 Zero-power sampling SAR ADC circuit and method 有权
标题翻译：零功率采样SAR ADC电路及方法
公开(公告)号：US20120280841A1
公开(公告)日：2012-11-08
申请号：US13068192
申请日：2011-05-04
申请人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
发明人： Yan Wang , Timothy V. Kalthoff , Michael A. Wu
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/1295 , H03M1/468
摘要： A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN−) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage. The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.
摘要翻译：开关电容器电路（10,32或32A）通过将加法导体（13）的顶板切换到第一参考电压（VSS）而将第一信号（VIN +）采样到第一电容器（C1或CIN1）上，并且将其底板切换到第一信号。将第二信号（VIN-）通过将其顶板切换到第二信号并将其底板切换到第一参考电压而被采样到第二电容器（C3或CIN3）上。在采样之后，第二电容器的顶板耦合到第一电容器的顶板。第二电容器的底板耦合到第一参考电压。第一电容器的底板耦合到第二参考电压（VDD或VREF），从而从第一导体（13）消除共模输入电压分量的至少一部分，将采样的差分电荷保持在求和并在其上建立预定的共模电压，并且防止求和导体具有允许从其中泄漏电荷的电压。开关电容电路可以是SAR，积分器或放大器。

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