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1. 发明申请

US20090006517A1 UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY 有权
标题翻译：统一整数/ GALOIS字段（2m）用于ELLIPTIC-CURVE CRYTPOGRAPHY的多用户体系结构
公开(公告)号：US20090006517A1
公开(公告)日：2009-01-01
申请号：US11772166
申请日：2007-06-30
申请人： VINODH GOPAL , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
发明人： VINODH GOPAL , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F17/00 , G06F7/52
CPC分类号： G06F7/72 , G06F7/5324 , G06F7/725 , G06F2207/382
摘要： A unified integer/Galois-Field 2m multiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The multiply operations may be performed on prime fields and different composite binary fields in independent multipliers in an interleaved fashion.
摘要翻译：统一的整数/伽罗瓦域2m乘法器为诸如Rivert，Shamir，Aldeman（RSA），Diffie-Hellman密钥交换（DH）和椭圆曲线加密系统（ECC）的公钥系统执行乘法运算。可以以交错方式在独立乘法器中的主场和不同的复合二进制字段上执行乘法运算。

2. 发明申请

US20140006536A1 TECHNIQUES TO ACCELERATE LOSSLESS COMPRESSION 审中-公开
标题翻译：加快无损压缩的技术
公开(公告)号：US20140006536A1
公开(公告)日：2014-01-02
申请号：US13538826
申请日：2012-06-29
申请人： JAMES D. GUILFORD , VINODH GOPAL , GILBERT M. WOLRICH , ERDINC OZTURK , WAJDI K. FEGHALI
发明人： JAMES D. GUILFORD , VINODH GOPAL , GILBERT M. WOLRICH , ERDINC OZTURK , WAJDI K. FEGHALI
IPC分类号： G06F15/16 , G06F15/167
CPC分类号： H03M7/60 , G06F9/30029 , H03M7/3068 , H03M7/6058
摘要： An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.
摘要翻译：实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置（b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组，与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中产生压缩数据流。描述和要求保护其他实施例。

3. 发明申请

US20140003602A1 Flexible Architecture and Instruction for Advanced Encryption Standard (AES) 审中-公开
标题翻译：高级加密标准（AES）的灵活架构和指令
公开(公告)号：US20140003602A1
公开(公告)日：2014-01-02
申请号：US14014091
申请日：2013-08-29
申请人： SHAY GUERON , WAJDI K. FEGHALI , VINODH GOPAL , MAKARAM RAGHUNANDAN , MARTIN G. DIXON , SRINIVAS CHENNUPATY , MICHAELE E. KOUNAVIS
发明人： SHAY GUERON , WAJDI K. FEGHALI , VINODH GOPAL , MAKARAM RAGHUNANDAN , MARTIN G. DIXON , SRINIVAS CHENNUPATY , MICHAELE E. KOUNAVIS
IPC分类号： H04L9/08
摘要： A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
摘要翻译：提供了一种用于通用处理器的灵活的指令集。指令集包括对aes加密或解密执行“一轮”通行的指令，还包括执行密钥生成的指令。立即可以用于指示128/192/256位键的密钥生成的循环数和密钥大小。灵活的aes指令集可以充分利用流水线功能，因为它不需要跟踪隐式寄存器。

4. 发明申请

US20140019764A1 METHOD FOR SIGNING AND VERIFYING DATA USING MULTIPLE HASH ALGORITHMS AND DIGESTS IN PKCS 有权
标题翻译：使用PKCS中的多个哈希算法和数据签名和验证数据的方法
公开(公告)号：US20140019764A1
公开(公告)日：2014-01-16
申请号：US13712401
申请日：2012-12-12
申请人： VINODH GOPAL , SEAN M. GULLEY , JAMES D. GUILFORD , WAJDI K. FEGHALI
发明人： VINODH GOPAL , SEAN M. GULLEY , JAMES D. GUILFORD , WAJDI K. FEGHALI
IPC分类号： H04L9/32
CPC分类号： H04L9/3247
摘要： Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed.
摘要翻译：公开了用于使用PKCS中的多个散列算法和摘要来签名和验证数据的方法，系统和装置，包括例如在起始计算设备处检索用于在始发计算设备处签名的消息以产生该消息的签名 ; 识别签名支持的多个散列算法; 对于被标识为被签名支持的多个散列算法中的每一个，散列消息以产生与识别的多个散列算法相对应的消息的多个哈希; 构建其中具有与识别的多个散列算法相对应的消息的多个散列中的每一个的单个摘要，并进一步指定要由签名支持的多个散列算法; 使用始发计算设备的私钥将签名算法应用于单个摘要以产生该消息的签名; 并将消息和签名分发给接收计算设备。公开了其他相关实施例。

5. 发明申请

US20130311756A1 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION WITHOUT READING CARRY FLAG 有权
标题翻译：完全执行无需阅读携带标志的指令
公开(公告)号：US20130311756A1
公开(公告)日：2013-11-21
申请号：US13947958
申请日：2013-07-22
申请人： VINODH GOPAL , JAMES D. GULILFORD , GILBERT M. WOLRICH , WAIDI K. FEGHALI , ERDINC OZTURK , MARTIN G. DIXON , SEAN P. MIRKES , BRET L. TOLL , MAXIM LOKTYUKHIN , MARK C. DAVIS , ALEXANDRE J. FARCY
发明人： VINODH GOPAL , JAMES D. GULILFORD , GILBERT M. WOLRICH , WAIDI K. FEGHALI , ERDINC OZTURK , MARTIN G. DIXON , SEAN P. MIRKES , BRET L. TOLL , MAXIM LOKTYUKHIN , MARK C. DAVIS , ALEXANDRE J. FARCY
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
摘要翻译：一个方面的方法可以包括接收旋转指令。旋转指令可以指示源操作数和旋转量。结果可以存储在由旋转指令指示的目标操作数中。结果可能使源操作数旋转了旋转量。旋转指令的执行可以在不读取进位标志的情况下完成。

6. 发明申请

US20150347231A1 TECHNIQUES TO EFFICIENTLY COMPUTE ERASURE CODES HAVING POSITIVE AND NEGATIVE COEFFICIENT EXPONENTS TO PERMIT DATA RECOVERY FROM MORE THAN TWO FAILED STORAGE UNITS 有权
标题翻译：有效地计算具有积极和负面的系统性能的有效代码的技术，允许数据恢复超过两个失败的存储单元
公开(公告)号：US20150347231A1
公开(公告)日：2015-12-03
申请号：US14293791
申请日：2014-06-02
申请人： VINODH GOPAL , ERDINC OZTURK
发明人： VINODH GOPAL , ERDINC OZTURK
IPC分类号： G06F11/10 , H03M13/15
CPC分类号： G06F11/1088 , G06F2211/1057 , H03M13/1515 , H03M13/159 , H03M13/373
摘要： Erasure code syndrome computation based on Reed Solomon (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of −1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x−1D of a syndrome is computed as a right-shift of data byte D, and selective compensation based on the most significant bit of D. Compensation may include bit-wise XORing shift results with a constant derived from an irreducible polynomial associated with the Galois field. A set of erasure code syndromes may be computed for each of multiple nested arrays of independent storage units. Data reconstruction includes solving coefficients of the syndromes as a Vandermonde matrix.
摘要翻译：基于Galois域中的Reed Solomon（RS）操作的擦除码校验子计算，以允许重建超过2个故障存储单元的数据。综合征计算可以用由-1，0和1组成的系数指数来执行。综合征的乘积xD被计算为数据字节D的左移，并且基于D的最高有效位的选择性补偿。综合征的乘积x-1D被计算为数据字节D的右移，并且基于D的最高有效位的选择性补偿。补偿可以包括具有从与不相关的多项式相关联的不可约多项式得到的常数的逐位异或移位结果伽罗瓦领域。可以为独立存储单元的多个嵌套阵列中的每一个计算一组擦除代码综合征。数据重建包括求解综合征的系数作为Vandermonde矩阵。

7. 发明申请

US20140019725A1 METHOD FOR FAST LARGE-INTEGER ARITHMETIC ON IA PROCESSORS 有权
标题翻译：用于IA处理器的快速大整数算术的方法
公开(公告)号：US20140019725A1
公开(公告)日：2014-01-16
申请号：US13707105
申请日：2012-12-06
申请人： ERDINC OZTURK , VINODH GOPAL , JAMES GUILFORD
发明人： ERDINC OZTURK , VINODH GOPAL , JAMES GUILFORD
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F7/52 , G06F7/523 , G06F7/544 , G06F9/30036 , G06F2207/5523
摘要： Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all sub-elements within their respective columns, the added sub-elements collectively identified as T2, and (v) yielding a final 512-bit squared result of the 512-bit value by adding the value of T2 twice with the value of T1 once. Other related embodiments are disclosed.
摘要翻译：公开了用于在诸如IA（Intel Architecture）处理器之类的集成电路内实现快速大整数运算的方法，系统和装置，其中这种装置包括接收512位的平方值，512位值具有八个子元素，每个64位，并通过以下方式执行512位平方算法：（i）将八个子元素中的每一个本身相乘以产生八个子元素中的每一个的平方，八个子元素 - 集体标识为T1的元件，（ii）将八个子元素中的每一个乘以八个子元素中的其余七个子元素以产生其中具有七个对角线的不对称中间结果，其中七个对角线中的每一个为（iii）将其中具有七个对角线的非对称中间结果重新组合成具有四个对角线的对称中间结果，每个对角线的长度为64位的7×1个子元素排列成跨越多个列，（iv）将其所有列中的所有子元素加入集体标识为T2的所添加的子元素，以及（v）通过将T2值增加两次来产生512位值的最终512位平方结果其T1值一次。公开了其他相关实施例。

8. 发明申请

US20140229807A1 INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS 审中-公开
标题翻译：可编程循环冗余检查（CRC）计算的指导体系结构
公开(公告)号：US20140229807A1
公开(公告)日：2014-08-14
申请号：US14254233
申请日：2014-04-16
申请人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
发明人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
IPC分类号： G06F11/10 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

9. 发明申请

US20100169401A1 FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION 有权
标题翻译：用于网络入侵和病毒检测的过滤器
公开(公告)号：US20100169401A1
公开(公告)日：2010-07-01
申请号：US12346734
申请日：2008-12-30
申请人： VINODH GOPAL , Christopher F. Clark , Gilbert Wolrich , Wajdi Feghali
发明人： VINODH GOPAL , Christopher F. Clark , Gilbert Wolrich , Wajdi Feghali
IPC分类号： G06F17/10
CPC分类号： H04L63/145 , G06F7/02 , G06F17/30949 , G06F17/30985 , G06F21/567 , G06F2207/025 , H04L63/0245 , H04L63/1416
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
摘要翻译：公开了对网络包检测进行字符串匹配的方法和装置。在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配结果。

10. 发明申请

US20130191699A1 INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS 有权
标题翻译：可编程循环冗余检查（CRC）计算的指导体系结构
公开(公告)号：US20130191699A1
公开(公告)日：2013-07-25
申请号：US13793358
申请日：2013-03-11
申请人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
发明人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
IPC分类号： H03M13/09
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

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