专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07814280B2 Shared-memory switch fabric architecture 有权
标题翻译：共享内存交换矩阵架构
公开(公告)号：US07814280B2
公开(公告)日：2010-10-12
申请号：US11208451
申请日：2005-08-18
申请人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
发明人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
IPC分类号： G06F12/00
CPC分类号： G11C7/1048 , G11C7/1075 , H04L49/101 , H04L49/103 , H04L49/351
摘要： A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory. The scheduling circuitry is further operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.
摘要翻译：描述了具有多个接收端口和以第一数据速率为特征的多个发送端口的共享存储器。存储器包括以行和列组织的多个存储器组。存储器阵列的操作的特征在于第二数据速率。非阻塞接收交叉开关电路可操作以将任何接收端口与任何存储器组连接。非阻塞发射交叉开关电路可操作以将任何存储体与任何发射端口连接。缓冲可操作以使第一数据速率处的接收和发送端口的操作与第二数据速率下的存储器阵列的操作分离。调度电路可操作以控制端口，交叉开关电路和存储器阵列的交互以实现共享存储器中的数据段的存储和检索。调度电路还可操作以便于跨越行中的一个存储体的帧的每个数据段的条带化，并且便于在阵列中的连续的行上对帧的连续数据段进行条带化。

2. 发明申请

US20100325370A1 SHARED-MEMORY SWITCH FABRIC ARCHITECTURE 审中-公开
标题翻译：共享开关织物结构
公开(公告)号：US20100325370A1
公开(公告)日：2010-12-23
申请号：US12862539
申请日：2010-08-24
申请人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
发明人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
IPC分类号： G06F12/02
CPC分类号： G11C7/1048 , G11C7/1075 , H04L49/101 , H04L49/103 , H04L49/351
摘要： A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is configured to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of frames of data in the shared memory by sequentially querying the plurality of ports for the frames of data, and arbitrating among a subset of the ports having the frames of data to assign starting locations in the memory banks such that the shared memory is fully provisioned for all of the ports simultaneously operating at the maximum port data rate.
摘要翻译：描述了具有多个接收端口和以第一数据速率为特征的多个发送端口的共享存储器。存储器包括以行和列组织的多个存储器组。存储器阵列的操作的特征在于第二数据速率。非阻塞接收交叉开关电路可操作以将任何接收端口与任何存储器组连接。非阻塞发射交叉开关电路可操作以将任何存储体与任何发射端口连接。缓冲可操作以使第一数据速率处的接收和发送端口的操作与第二数据速率下的存储器阵列的操作分离。调度电路被配置为控制端口，交叉开关电路和存储器阵列的交互，以通过对多个端口顺序地查询数据帧来实现对共享存储器中的数据帧的存储和检索，并且在具有数据帧的端口，以分配存储器组中的起始位置，使得共享存储器被完全配置为以最大端口数据速率同时工作的所有端口。

3. 发明申请

US20060155938A1 Shared-memory switch fabric architecture 有权
标题翻译：共享内存交换矩阵架构
公开(公告)号：US20060155938A1
公开(公告)日：2006-07-13
申请号：US11208451
申请日：2005-08-18
申请人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
发明人： Uri Cummings , Andrew Lines , Patrick Pelletier , Robert Southworth
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G11C7/1048 , G11C7/1075 , H04L49/101 , H04L49/103 , H04L49/351
摘要： A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory. The scheduling circuitry is further operable to facilitate striping of each data segment of a frame across the memory banks in one of the rows, and to facilitate striping of successive data segments of the frame across successive rows in the array.
摘要翻译：描述了具有多个接收端口和以第一数据速率为特征的多个发送端口的共享存储器。存储器包括以行和列组织的多个存储器组。存储器阵列的操作的特征在于第二数据速率。非阻塞接收交叉开关电路可操作以将任何接收端口与任何存储器组连接。非阻塞发射交叉开关电路可操作以将任何存储体与任何发射端口连接。缓冲可操作以使第一数据速率处的接收和发送端口的操作与第二数据速率下的存储器阵列的操作分离。调度电路可操作以控制端口，交叉开关电路和存储器阵列的交互以实现共享存储器中的数据段的存储和检索。调度电路还可操作以便于跨越行中的一个存储体的帧的每个数据段的条带化，并且便于在阵列中的连续的行上对帧的连续数据段进行条带化。

4. 发明授权

US07698535B2 Asynchronous multiple-order issue system architecture 失效
标题翻译：异步多阶问题系统架构
公开(公告)号：US07698535B2
公开(公告)日：2010-04-13
申请号：US10667152
申请日：2003-09-16
申请人： Andrew Lines , Robert Southworth , Uri Cummings
发明人： Andrew Lines , Robert Southworth , Uri Cummings
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3885
摘要： An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
摘要翻译：描述了用于处理具有与其相关联的程序顺序的数据单元的异步电路。该电路包括N路并行流水线的N路发行资源。每个流水线可操作地以先进先出的方式传输数据单元的子集。异步电路可操作以顺序地控制管道中的数据单元的传输，从而保持程序顺序。

5. 发明授权

US07274710B2 Asynchronous crossbar with deterministic or arbitrated control 有权
标题翻译：具有确定性或仲裁控制的异步交叉开关
公开(公告)号：US07274710B2
公开(公告)日：2007-09-25
申请号：US10237406
申请日：2002-09-06
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J3/02
CPC分类号： H04Q3/0004
摘要： Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
摘要翻译：描述了涉及可操作以根据路由控制信息将数据从第一数量的输入信道中的任何一个路由到第二数量的输出信道中的任一个的交叉开关的方法和装置。输入通道和输出通道的每个组合对应于多个链接中的一个。交叉开关电路可操作地以确定性的方式在每个链路上路由数据，从而保留由路由控制信息表示的部分排序。不同链接的事件是不相关的。

6. 发明授权

US07161828B2 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US07161828B2
公开(公告)日：2007-01-09
申请号：US11200722
申请日：2005-08-09
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件。

7. 发明申请

US20060239392A1 Asynchronous system-on-a-chip interconnect 审中-公开
标题翻译：异步片上系统互连
公开(公告)号：US20060239392A1
公开(公告)日：2006-10-26
申请号：US11472984
申请日：2006-06-21
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04L7/00
CPC分类号： G06F13/423 , G06F1/12 , G06F2213/0038 , H04L7/005 , H04L7/02 , H04L49/101 , H04L2012/5674 , H04Q3/0004 , H04Q2213/13034 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/13361 , H04Q2213/13362
摘要： Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要翻译：描述了涉及包括多个同步模块的片上系统的方法和装置，每个同步模块具有由数据速率表征的相关联的时钟域，数据速率包括多个不同的数据速率。片上系统还包括多个时钟域转换器。每个时钟域转换器被耦合到对应的一个同步模块，并且可操作以在对应的同步模块的时钟域和根据异步握手协议的数据传输特征的异步域之间转换数据。异步交叉开关耦合到多个时钟域转换器，并且可在异步域中操作以实现任何两个时钟域转换器之间的先进先出（FIFO）通道，从而促进任何两个时钟域转换器之间的通信同步模块。

8. 发明授权

US06658550B2 Pipelined asynchronous processing 有权
公开(公告)号：US06658550B2
公开(公告)日：2003-12-02
申请号：US10137035
申请日：2002-04-30
申请人： Alain J. Martin , Andrew Lines , Rajit Manohar , Uri Cummings , Mika Nystroem
发明人： Alain J. Martin , Andrew Lines , Rajit Manohar , Uri Cummings , Mika Nystroem
IPC分类号： G06F900
CPC分类号： G06F15/8053 , G06F9/3824 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F9/3863 , G06F9/3871 , G06F12/0855
摘要： An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

9. 发明授权

US07050324B2 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US07050324B2
公开(公告)日：2006-05-23
申请号：US10890816
申请日：2004-07-13
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件，只要满足至少一个定时假设即可。

10. 发明申请

US20050024928A1 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US20050024928A1
公开(公告)日：2005-02-03
申请号：US10890816
申请日：2004-07-13
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C20060101 , G11C11/00 , G11C11/413 , G11C15/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件，只要满足至少一个定时假设即可。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式